HYS64T128020GU-37-A

Manufacturer Part NumberHYS64T128020GU-37-A
Description240-Pin Unbuffered DDR2 SDRAM Modules
ManufacturerINFINEON [Infineon Technologies AG]
HYS64T128020GU-37-A datasheet
 


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D a t a S h e e t , Rev. 0.87, J u n e 2 0 0 4
HYS64T32000[G/H]U–[3.7/5]–A
HYS[64/72]T64000[G/H]U–[3.7/5]–A
HYS[64/72]T128020[G/H]U–[3.7/5]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
M e m o r y P r o d u c t s
N e v e r
s t o p
t h i n k i n g .

HYS64T128020GU-37-A Summary of contents

  • Page 1

    ... HYS64T32000[G/H]U–[3.7/5]–A HYS[64/72]T64000[G/H]U–[3.7/5]–A HYS[64/72]T128020[G/H]U–[3.7/5]–A 240-Pin Unbuffered DDR2 SDRAM Modules DDR2 SDRAM Rev. 0.87 ...

  • Page 2

    The information in this document is subject to change without notice. Edition 2004-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe ...

  • Page 3

    ... HYS64T32000[G/H]U–[3.7/5]–A HYS[64/72]T64000[G/H]U–[3.7/5]–A HYS[64/72]T128020[G/H]U–[3.7/5]–A 240-Pin Unbuffered DDR2 SDRAM Modules DDR2 SDRAM Rev. 0.87 ...

  • Page 4

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Revision History: Rev. 0.87 Previous Revision: Rev. 0.84 Page Subjects (major changes since last revision) all New template chapter 5 add currents all updated timings We Listen to Your Comments Any information within this document that you feel is ...

  • Page 5

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    ... HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A 1 Overview This chapter gives an overview of the 1.8 V 240-pin Unbuffered DDR2 SDRAM Modules, 256 MByte, 512 MByte & 1 GByte ECC and non-ECC Modules and describes its main characteristics. 1.1 Features • 240-pin ECC and Non-ECC Unbuffered 8-Byte Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications • ...

  • Page 7

    ... HYS64T64000GU–3.7–A 512MB 1R×8 PC2–4200U–444–11–A0 HYS72T64000GU–3.7–A 512MB 1R×8 PC2–4200E–444–11–A0 HYS64T128020GU–3.7–A 1GB 2R×8 PC2–4200U–444–11–B0 HYS72T128020GU–3.7–A 1GB 2R×8 PC2–4200E–444–11–B0 HYS64T32000HU–3.7–A 256MB 1R× ...

  • Page 8

    ... MB 2) HYS64T32000HU 256 MB HYS64T64000GU 512 MB 2) HYS64T64000HU 512 MB HYS72T64000GU 512 MB 2) HYS72T64000HU 512 MB HYS64T128020GU HYS64T128020HU 1 GB HYS72T128020GU HYS72T128020HU For a detailed description of all functionalities of the DRAM components on these modules see the referenced component datasheet. 2) Green Product Data Sheet ...

  • Page 9

    ... Control Signals 193 76 192 74 73 Address Signals 71 190 54 188 183 63 182 61 60 180 58 179 177 Data Sheet for non-ECC modules (×64) and Name Pin Buffer Function Type Type CK0 I SSTL Clock Signals 2:0 CK1 I SSTL CK2 I SSTL CK0 I SSTL Complement Clock Signals 2:0 CK1 ...

  • Page 10

    ... Note: 1 Gbit based module and 512M NC NC — Note: 1. Module based on 1 Gbit 2. Module based on 512 Mbit A14 I SSTL Address Signal 14 Note: Modules based on 2 Gbit NC NC — Note: Modules based on 1 Gbit or smaller DQ0 I/O SSTL Data Bus 63:0 DQ1 I/O SSTL DQ2 I/O SSTL DQ3 I/O SSTL DQ4 ...

  • Page 11

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 5 Pin Configuration of UDIMM (cont’d) Pin 152 153 158 159 199 200 205 206 208 209 214 215 98 99 107 108 217 218 226 227 110 ...

  • Page 12

    ... CB5 I/O SSTL Check Bit 5 Note: ECC type module only NC NC — Note: Non-ECC module CB6 I/O SSTL Check Bit 6 Note: ECC type module only NC NC — Note: Non-ECC module CB7 I/O SSTL Check Bit 7 Note: ECC type module only NC NC — Note: Non-ECC module ...

  • Page 13

    ... DDQ V PWR — Power Supply DD V GND — Ground Plane SS ODT0 On-Die Termination Control 0 ODT1 On-Die Termination Control 1 Note: 1 Rank modules NC NC — — Not connected Note: Pins not connected on Infineon UDIMMs 13 512 Mbit DDR2 SDRAM Overview Rev. 0.87, 2004-06 09122003-GZEK-H4J6 ...

  • Page 14

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 6 Abbreviations for Buffer Type Abbreviation I O I/O AI PWR GND NC Table 7 Abbreviations for Buffer Type Abbreviation SSTL LV-CMOS CMOS OD Data Sheet Description Standard input-only pin. Digital levels. Output. Digital levels. I ...

  • Page 15

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A VREF - Pin 001 V SS DQ0 - Pin 003 DQ1 V - Pin 005 SS DQS0 DQS0 - Pin 007 V SS DQ2 - Pin 009 DQ3 V - Pin 011 SS DQ8 DQ9 - Pin 013 V ...

  • Page 16

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A VREF - Pin 001 DQ0 - Pin 003 DQ1 - V - Pin 005 SS DQS0 - DQS0 - Pin 007 DQ2 - Pin 009 DQ3 - V - Pin 011 SS DQ8 ...

  • Page 17

    ... In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module operated in single ended strobe mode, all DQS signals must be tied on the system board to resistor and DDR2 SDRAM mode registers programmed appropriately ...

  • Page 18

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A 2 Block Diagrams %$  %$ 6'5$ %$  %$ $  $ $Q 6'5$ 5$6 5$6 6'5$ &$6 &$6 6'5$ :( 6'5$0V ' ...

  • Page 19

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A %$  %$ %$  %$ 6'5$ $Q 6'5$ 5$6 5$6 6'5$ &$6 6'5$ &$6 :( 6'5$ &.( ...

  • Page 20

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A ) BA0 - BA2 BA0 - BA2: SDRAMs D0 - D15 An: SDRAMs D0 - D15 RAS RAS: SDRAMs D0 - D15 CAS CAS: SDRAMs D0 - D15 WE WE: SDRAMs D0 - D15 ...

  • Page 21

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A &.(  &.(  6'5$ &.(  &.(  6'5$ ' 2'7  2'7  6'5$ 2'7  2'7  6'5$ ' '0 '0 &6 ...

  • Page 22

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A %$  %$ %$  %$ 6'5$ $Q 6'5$ 5$6 5$6 6'5$ &$6 &$6 6'5$ :( 6'5$ &.( ...

  • Page 23

    ... Table 14 Operating Conditions Parameter DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Barometric Pressure (operating & storage) 1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs ...

  • Page 24

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]– Specifications and Conditions DD I Table 16 Measurement Conditions DD Parameter Operating Current 0 One bank Active - Precharge valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING Operating Current 1 One ...

  • Page 25

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 16 I Measurement Conditions DD Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. max. All ...

  • Page 26

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A I Table 18 Specification DD Product Type Organization 256MB 512MB ×64 ×64 1 Rank 1 Rank –5 –5 Symbol Max. Max. I 280 DD0 I 300 DD1 I 16 DD2P I 128 DD2F I 100 DD2Q I 52 DD3P( ...

  • Page 27

    ... Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval 1) For modules based on x8 components 2) For modules based on x16 components 4.2 ODT (On Die Termination) Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & the EMRS(1) a “week” or “strong” termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tristate or driving long a ODT is enabled during a given period of time ...

  • Page 28

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A 5 Electrical Characteristics & AC Timings 5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only) Table 21 AC Timing - Absolute Specifications –5 / –3.7 Symbol Parameter t DQ output access time from CK/CK AC ...

  • Page 29

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 21 AC Timing - Absolute Specifications –5 / –3.7 Symbol Parameter t Average Periodic Refresh REFI Interval t Auto-refresh to Active/Auto-refresh command RFC period t Precharge command period RP t Read preamble RPRE t Read postamble RPST t ...

  • Page 30

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 22 ODT AC Electrical Characteristics and Operating Conditions (all speed bins) Symbol Parameter / Condition t ODT to Power Down Mode Entry Latency ANPD t ODT turn-off AOF t ODT turn-off delay AOFD t ODT turn-off delay (Power-Down ...

  • Page 31

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A 6 SPD Codes Table 23 SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of ...

  • Page 32

    ... SPD Codes for HYS[64/72]T[32/64]000GU–3.7–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RP.min t 28 [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min t 35 [ns] DH.min t ...

  • Page 33

    ... T 61 (DTREG) / Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon ( JEDEC ID Code of Infineon ( Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 ...

  • Page 34

    ... Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 -127 Not Used 128- BLANK 255 Data Sheet 512 Mbit DDR2 SDRAM 256 MB 512 MB × ...

  • Page 35

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 24 SPD Codes HYS[64/72]T128020GU–3.7–A Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number ...

  • Page 36

    ... SPD Codes HYS[64/72]T128020GU–3.7–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RP.min 28 t [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min t 35 [ns] DH.min t ...

  • Page 37

    ... Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon ( JEDEC ID Code of Infineon ( Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 ...

  • Page 38

    ... Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 -127 Not Used 128-255 BLANK Data Sheet 512 Mbit DDR2 SDRAM 1 GByte ×64 2 Ranks (× ...

  • Page 39

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 25 SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 ...

  • Page 40

    ... Table 25 SPD Codes for HYS[64/72]T[32/64]000HU–3.7–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 28 [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min t 35 [ns] DH ...

  • Page 41

    ... Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon ( JEDEC ID Code of Infineon ( Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 ...

  • Page 42

    ... Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 -127 Not Used 128-255 BLANK Data Sheet 512 Mbit DDR2 SDRAM 256 MB 512 MB × ...

  • Page 43

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 26 SPD Codes for HYS[64/72]T128020HU–3.7–A Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 ...

  • Page 44

    ... SPD Codes for HYS[64/72]T128020HU–3.7–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RP.min t 28 [ns] RRD.min t 29 [ns] RCD.min 30 t [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min t 35 [ns] DH.min t ...

  • Page 45

    ... Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon ( JEDEC ID Code of Infineon ( Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 ...

  • Page 46

    ... Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 -127 Not Used 128-255 BLANK Data Sheet 512 Mbit DDR2 SDRAM 1 GByte ×64 2 Ranks (× ...

  • Page 47

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 27 SPD Codes for HYS[64/72]T32000GU–5–A Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 ...

  • Page 48

    ... Table 27 SPD Codes for HYS[64/72]T32000GU–5–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 28 [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min t 35 [ns] DH ...

  • Page 49

    ... Product Type, Char 14 87 Product Type, Char 15 88 Product Type, Char 16 89 Product Type, Char 17 90 Product Type, Char 18 91 Module Revision Code Data Sheet 512 Mbit DDR2 SDRAM 256 MB 512 MB ×64 ×64 1 Rank (×16) 1 Rank (×8) PC2–3200U–333 Rev. 1.1 Rev ...

  • Page 50

    ... Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 -127 Not Used 128-255 BLANK Table 28 SPD Codes for HYS[64/72]T128020GU–5–A Product Type ...

  • Page 51

    ... SDRAM @ CL -2 [ns] AC max t 27 [ns] RP.min t 28 [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank Data Sheet 512 Mbit DDR2 SDRAM 1 GByte ×64 2 Ranks (×8) PC2–3200U–333 Rev. 1.1 HEX ...

  • Page 52

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 28 SPD Codes for HYS[64/72]T128020GU–5–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min t 35 [ns] DH.min ...

  • Page 53

    ... Product Type, Char 15 88 Product Type, Char 16 89 Product Type, Char 17 90 Product Type, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year Data Sheet 512 Mbit DDR2 SDRAM 1 GByte ×64 2 Ranks (×8) PC2–3200U–333 Rev. 1.1 HEX ...

  • Page 54

    ... Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 -127 Not Used 128-255 BLANK Table 29 SPD Codes for HYS[64/72]T[32/64]000HU–5–A Product Type Organization Label Code JEDEC SPD Revision ...

  • Page 55

    ... CL -2 (Byte 18) [ns] CK max t 26 SDRAM @ CL AC max 27 t [ns] RP.min t 28 [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min Data Sheet (Byte 18) [ns] -1 [ns] -2 [ns] 55 512 Mbit DDR2 SDRAM 256 MB ...

  • Page 56

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 29 SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 35 [ns] DH.min t 36 [ns] WR.min t 37 [ns] WTR.min t 38 [ns] RTP.min 39 Analysis Characteristics ...

  • Page 57

    ... Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) Data Sheet 512 Mbit DDR2 SDRAM 256 MB 512 MB ×64 ×64 1 Rank (×16) 1 Rank (× ...

  • Page 58

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 29 SPD Codes for HYS[64/72]T[32/64]000HU–5–A (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description 99 -127 Not Used 128-255 BLANK Table 30 SPD Codes for HYS[64/72]T128020HU–5–A Product Type Organization Label Code JEDEC SPD Revision Byte# Description ...

  • Page 59

    ... SDRAM @ CL AC max (Byte 18) [ns] CK max 26 t SDRAM @ CL AC max t 27 [ns] RP.min t 28 [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] DS.min t 35 [ns] DH.min t 36 [ns] WR.min t 37 [ns] WTR.min t 38 [ns] RTP ...

  • Page 60

    ... PLL ∆ (DTREG) / Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon ( JEDEC ID Code of Infineon ( Module Manufacturer Location Data Sheet Delta 4R4W T (DT2Q, RDIMM Sign (DT4R4W) 60 512 Mbit DDR2 SDRAM SPD Codes 1 GByte 1 GByte ×64 ×72 2 Ranks (×8) 2 Ranks (× ...

  • Page 61

    ... Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 -127 Not Used 128-255 BLANK Data Sheet 512 Mbit DDR2 SDRAM 1 GByte ×64 2 Ranks (× ...

  • Page 62

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A 7 Package Outlines 7.1 Raw Card ±0.1 121 3 MIN. Detail of contacts 1 0.8 ±0.2 Burr max. 0.4 allowed Figure 8 Package Outline L-DIM-240-1 Data Sheet 133.35 128.95 ±0.1 4 ±0.1 2.5 ±0.1 5 ±0.1 ...

  • Page 63

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A 7.2 Raw Card ±0.1 121 3 MIN. Detail of contacts 1 0.8 ±0.2 Burr max. 0.4 allowed Figure 9 Package Outline L-DIM-240-2 Data Sheet 133.35 128.95 ±0.1 4 ±0.1 2.5 ±0.1 5 ±0 1.5 ...

  • Page 64

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A 7.3 Raw Card 121 (3) Detail of contacts 1 0.8 ±0.05 Burr max. 0.4 allowed Figure 10 Package Outline L-DIM-240-3 Data Sheet 133.35 128. 1.5 ±0.1 0 512 ...

  • Page 65

    ... Speed Grade 11 Die Revision 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Data Sheet Product Type Nomenclature (DDR2 DRAMs and DIMMs) ...

  • Page 66

    HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A Table 33 DDR2 DRAM Nomenclature Field Description 1 INFINEON Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component Density [Mbit] 5+6 Number of I/Os 7 Product Variations 8 Die Revision 9 Package, Lead-Free Status 10 Speed Grade ...

  • Page 67

    Published by Infineon Technologies AG ...