HYS64T128020HU-5-B QIMONDA [Qimonda AG], HYS64T128020HU-5-B Datasheet - Page 20

• Manufacturer Part Number: HYS64T128020HU-5-B
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until V
4) The output timing reference voltage level is V
5) t
3.3.2
Timing Parameters for:
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Parameter
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
input reference level is the crosspoint when in differential strobe mode
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t
Component AC Timing Parameters
DDR2–800(Table
@ CL = 3
@ CL = 4
@ CL = 5
REF
16),
stabilizes. During the period before V
TT
.
DRAM Component Timing Parameter by Speed Grade - DDR2–800
DDR2–667(Table
Symbol
t
t
t
t
t
t
t
t
t
AC
CCD
CH.AVG
CK.AVG
CKE
CL.AVG
DAL
DELAY
DH.BASE
Symbol
t
t
t
t
t
t
t
CK
CK
CK
RAS
RC
RCD
RP
20
Speed Grade Definition Speed Bins for DDR2-400B
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
17),
DDR2–800
–400
2
0.48
2500
3
0.48
WR +
t
t
125
Min.
IS
IH
DDR2–533C(Table
+
t
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
CK .AVG
t
nRP
REF
stabilizes, CKE = 0.2 x V
+
Max.
8
8
8
70000
—
—
—
Max.
+400
—
0.52
8000
—
0.52
—
––
––
Unbuffered DDR2 SDRAM Module
18) and
DDR2–400B(Table
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
Unit
ps
nCK
t
ps
nCK
t
nCK
ns
ps
CK.AVG
CK.AVG
DDQ
Internet Data Sheet
is recognized as low.
TABLE 15
TABLE 16
Note
1)2)3)4)5)6)7)8)
9)
10)11)
10)11)
12)
10)11)
13)14)
19)20)15)
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
19)
REFI
.