CDP1883CE INTERSIL [Intersil Corporation], CDP1883CE Datasheet

CDP1883CE

Manufacturer Part Number

CDP1883CE

Description

CMOS 7-Bit Latch and Decoder Memory Interfaces

Manufacturer

INTERSIL [Intersil Corporation]

Datasheet

1.CDP1883CE.pdf (6 pages)

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Download datasheet (36Kb)

March 1997

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Features

• Performs Memory Address Latch and Decoder Func-

• Interfaces Directly with the CDP1800-Series Micropro-

• Allows Decoding for Systems Up to 32K Bytes

Ordering Information

Pinout

CDP1883CE CDP1883E

tions Multiplexed or Non-Multiplexed

cessors

10V

-40

RANGE

TEMP.

+85

C to

PDIP

PACKAGE

Intersil Corporation 1999

CLOCK

MA0

MA1

MA2

MA3

MA4

MA5

MA6

E20.3

CDP1883, CDP1883C

PKG.

NO.

TOP VIEW

(PDIP)

4-129

Description

The CDP1883 is a CMOS 7-bit memory latch and decoder

circuit intended for use in CDP1800-series microprocessor

systems. It can serve as a direct interface between the multi-

plexed address bus of this system and up to four 8K x 8-bit

memories to implement a 32K-byte memory system. With

four 4K x 8-bit memories, a 16K-byte system can be

decoded.

The device is also compatible with non-multiplexed address

bus microprocessors. By connecting the clock input to V

the latches are in the data-following mode and the decoded

outputs can be used in general-purpose memory-system

applications.

The CDP1833 is compatible with CDP1800-series micropro-

cessors operating at maximum clock frequency.

The CDP1883 and CDP1883C are functionally identical.

They differ in that the CDP1883 has a recommended operat-

ing voltage range of 4V to 10.5V and the C version has a

recommended operating voltage range of 4V to 6.5V.

The CDP1883 and CDP1883C are supplied in 20 lead dual-

in-line plastic packages (E Sufﬁx).

A10

A11

A12

CS0

CS1

CS2

CS3

and Decoder Memory Interfaces

CDP1883C

CDP1883,

CMOS 7-Bit Latch

File Number

1507.2

Related parts for CDP1883CE

CDP1883CE Summary of contents

Page 1

... Interfaces Directly with the CDP1800-Series Micropro- cessors • Allows Decoding for Systems Up to 32K Bytes Ordering Information TEMP. 5V 10V RANGE o CDP1883CE CDP1883E - +85 C Pinout CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | http://www.intersil.com or 407-727-9207 ...

Page 2

Absolute Maximum Ratings DC Supply Voltage Range (All Voltages Referenced to V Terminal) SS CDP1883 . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

Static Electrical Speciﬁcations V O PARAMETER SYMBOL (V) Minimum Data V DR Retention Voltage Data Retention Current I DR Input Capacitance Output Capacitance C - OUT NOTES Typical values are for T = +25 C. ...

Page 4

Signal Descriptions/Pin Functions CLOCK: Latch Input Control - a high on the clock input will allow data to pass through the latch to the output pin. Data is latched on the high-to-low transition of the clock input. This pin is ...

Page 5

Dynamic Electrical Speciﬁcations PARAMETER CLOCK to Address Memory Address to Chip Select Memory Address to Address NOTES Typical values are for Maximum limits of minimum characteristics are the values above which all ...

Page 6

WAIT TPA CDP1800 CLR SERIES CPU MRD MWR FIGURE 2. MINIMUM CDP1800-SYSTEM USING THE CDP1883 INTERFACE WITH 8-BIT MEMORY CDP1883 LATCH/ DECODER CS3 CLK CS2 CS1 CE CS0 MA0 - MA6 A8 - A12 WAIT CLR A8 ...

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