PEEL22CV10A ANACHIP [Anachip Corp], PEEL22CV10A Datasheet

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PEEL22CV10A

Manufacturer Part Number
PEEL22CV10A
Description
CMOS Programmable Electrically Erasable Logic Device
Manufacturer
ANACHIP [Anachip Corp]
Datasheet

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This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.
Features
General Description
The PEEL™22CV10A is a Programmable Electrically Eras-
able Logic (PEEL™) device providing an attractive alterna-
tive to ordinary PLDs. The PEEL™22CV10A offers the
performance, flexibility, ease of design and production
practicality
PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP
and 28-pin PLCC packages (see Figure 1), with speeds
ranging from 7ns to 25ns and with power consumption as low
as 30mA. EE-reprogrammability provides the conve- nience
of instant reprogramming for development and a reusable
production
programming changes or errors. EE-reprogrammability
Figure 1. Pin Configuration
DIP
*Optional extra ground pin for
PLCC
-7/I-7 speed grade.
High Speed/Low Power
Electrically Erasable Technology
Development/Programmer Support
- Speeds ranging from 7ns to 25ns
- Power as low as 30mA at 25MHz
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
- Third party software and programmers
- Anachip PLACE Development Software
CMOS Programmable Electrically Erasable Logic Device
needed
inventory,
9
by
minimizing
I/CLK
TSSOP
GND
logic
I
I
I
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
PEEL™ 22CV10A -7/-10/-15/-25
designers
SOIC
the
24
23
22
21
20
19
18
17
16
15
14
13
today.
impact
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
The
of
1/10
Figure 2. Block Diagram
also improves factory testability, thus ensuring the highest
quality possible. The PEEL™22CV10A is JEDEC file com-
patible with standard 22V10 PLDs. Eight additional configu-
rations per macrocell (a total of 12) are also available by
using the “+” software/programming option (i.e., 22CV10A+
& 22CV10A++). The additional macrocell configurations
allow more logic to be put into every design. Programming
and development support for the PEEL™22CV10A are pro-
vided by popular third-party programmers and develop-
ment
development software.
Architectural Flexibility
Application Versatility
- 132 product term X 44 input AND array
- Up to 22 inputs and 10 outputs
- Up to 12 configurations per macrocell
- Synchronous preset, asynchronous clear
- Independent output enables
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Enhanced Architecture fits more logic
than ordinary PLDs
software.
Anachip
also
offers
Rev. 1.0 Dec 16, 2004
free
PLACE

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PEEL22CV10A Summary of contents

Page 1

CMOS Programmable Electrically Erasable Logic Device Features High Speed/Low Power - Speeds ranging from 7ns to 25ns - Power as low as 30mA at 25MHz Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit ...

Page 2

Anachip Corp. www.anachip.com.tw 2/10 Rev. 1.0 Dec 16, 2004 ...

Page 3

Function Description The PEEL™22CV10A implements logic functions as sum- of-products expressions in a programmable-AND/ fixed-OR logic array. User-defined functions are created by program- ming the connections of input signals into the array. User- configurable output structures in the form of ...

Page 4

... PEEL™22CV10AZ. maintain JEDEC file compatibility with standard 22V10 PLDs the additional configurations can only be utilized by specifying the PEEL™22CV10A+ and PEEL22CV10A++ for logic assembly and programming. To reference these additional configurations please refer to the specifications at the end of this data sheet. ...

Page 5

Figure 5. Four Configurations of the PEEL™22CV10A I/O Macrocell Table 1. PEEL™ 22CV10A Macrocell Configuration Bits Configuration # Anachip Corp. www.anachip.com.tw Input/Feedback Select Register Feedback Bi-Directional ...

Page 6

... Besides the standard four-configuration macrocells, each PEEL™22CV10A provides an additional eight configura- tions (twelve total) that can be used to increase design flex- ibility Figure 6. Twelve Configurations of the PEEL™22CV10A+ and PEEL22CV10A++ I/O Macrocell Table 2. PEEL™ 22CV10A+ & A++ Macrocell Configuration Bits Configuration # ...

Page 7

Table 6. Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin Output Current O T Storage Temperature ST T Lead Temperature LT Table 7. Operating Ranges Symbol Parameter V ...

Page 8

Table 9. A.C. Electrical Characteristics Symbol Parameter 5 Input to non-registered output Input to output enable Input to output disable t OD Clock to Output t CO1 Clock to comb. output delay ...

Page 9

... Table 6. Ordering Information Part Number PEEL22CV10AP-7 (L) PEEL22CV10API-7 (L) PEEL 22CV10AJ-7 (L) PEEL 22CV10AJI-7 (L) PEEL 22CV10AS-7 (L) PEEL 22CV10ASI-7 (L) PEEL 22CV10AT-7 (L) PEEL 22CV10ATI-7 (L) PEEL 22CV10AP-10 (L) PEEL 22CV10API-10 (L) PEEL 22CV10AJ-10 (L) PEEL 22CV10AJI-10 (L) PEEL 22CV10AS-10 (L) PEEL 22CV10ASI-10 (L) PEEL 22CV10AT-10 (L) PEEL 22CV10ATI-10 (L) PEEL 22CV10AP-15 (L) PEEL 22CV10API-15 (L) PEEL 22CV10AJ-15 (L) ...

Page 10

Part Number Package P = Plastic 300 mil DIP J = Plastic (J) Leaded Chip Carrier (PLCC SOIC T = TSSOP Anachip Corp. Head Office 2F, No. 24-2, Industry E. Rd. IV, Science-Based Industrial Park, Hsinchu, 300, Taiwan ...

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