MC54-74HC175 MOTOROLA [Motorola, Inc], MC54-74HC175 Datasheet

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MC54-74HC175

Manufacturer Part Number
MC54-74HC175
Description
Quad D Flip-Flop with Common Clock and Reset
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
inputs, and separate D inputs. Reset (active–low) is asynchronous and
occurs when a low level is applied to the Reset input. Information at a D input
is transferred to the corresponding Q output on the next positive going edge
of the Clock input.
10/95
INPUTS
Motorola, Inc. 1995
DATA
The MC54/74HC175 is identical in pinout to the LS175. The device inputs
This device consists of four D flip–flops with common Reset and Clock
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 166 FETs or 41.5 Equivalent Gates
CLOCK
D0
D1
D2
D3
RESET
12
13
9
4
5
1
PIN 16 = V CC
PIN 8 = GND
LOGIC DIAGRAM
10
15
14
11
2
3
7
6
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
NONINVERTING
INVERTING
OUTPUTS
AND
1
REV 6
16
MC54/74HC175
16
16
1
Reset Clock
1
RESET
H
H
H
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
L
ORDERING INFORMATION
1
GND
Q0
Q0
Q1
Q1
D0
D1
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
X
L
1
2
3
4
5
6
7
8
CERAMIC PACKAGE
D
X
H
X
PLASTIC PACKAGE
L
SOIC PACKAGE
CASE 751B–05
CASE 620–10
CASE 648–08
16
15
14
13
12
10
11
9
No Change
N SUFFIX
D SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
Outputs
Q
H
L
L
V CC
Q3
Q3
D3
D2
Q2
Q2
CLOCK
Q
H
H
L

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MC54-74HC175 Summary of contents

Page 1

... Quad D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC54/74HC175 is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of four D flip–flops with common Reset and Clock inputs, and separate D inputs. Reset (active– ...

Page 2

... MC54/74HC175 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

... MC54/74HC175 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... MC54/74HC175 90% CLOCK 50% 10 1/f max t PLH t PHL 90 50% 10% t TLH t THL Figure 1. CLOCK MOTOROLA SWITCHING WAVEFORMS V CC RESET GND Q Q CLOCK VALID DATA 50% Figure 3. TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 4 ...

Page 5

... D0 9 CLOCK RESET High–Speed CMOS Logic Data DL129 — Rev 6 EXPANDED LOGIC DIAGRAM MC54/74HC175 MOTOROLA ...

Page 6

... MC54/74HC175 –A – –T – SEATING PLANE 0.25 (0.010) M –A – 0.25 (0.010) –A – –T – SEATING PLANE 0.25 (0.010 MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620–10 ISSUE V – ...

Page 7

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MC54/74HC175/D* 7 MC54/74HC175 MC54/74HC175/D MOTOROLA ...

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