PEEL22LV10AZTI-25 ETC2 [List of Unclassifed Manufacturers], PEEL22LV10AZTI-25 Datasheet

PEEL22LV10AZTI-25

Manufacturer Part Number

PEEL22LV10AZTI-25

Description

CMOS Programmable Electrically Erasable Logic Device

Manufacturer

ETC2 [List of Unclassifed Manufacturers]

Datasheet

1.PEEL22LV10AZTI-25.pdf (10 pages)

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Features

General Description

The PEEL22LV10AZ is a Programmable Electrically

Erasable Logic (PEEL) SPLD (Simple Programmable

Logic Device) that operates over the supply voltage

range of 2.7V-3.6V and features ultra-low, automatic

"zero" power-down operation. The PEEL22LV10AZ is

logically

PEEL22CV10A and PEEL22CV10AZ. The "zero power"

(25

PEEL22LV10AZ ideal for a broad range of battery-

powered portable equipment applications, from hand-

held

reprogrammability provides both the convenience of

product fast reprogramming for product development

and quick personalization in manufacturing, including

Engineering Change Orders.

Figure 1 - Pin Configuration

I/CLK

DIP

PLCC

G ND

Low Voltage, Ultra Low Power Operation

- Vcc = 2.7 to 3.6 V

- Icc = 5 µA (typical) at standby

- Icc = 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JESD8-B)

- 5 Volt tolerant inputs and I/O’s

CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

Application Versatility

- Replaces random logic

- Super set of standard PLDs

- Pin and JEDEC compatible with 22V10

- Ideal for battery powered systems

- Replaces expensive oscillators

A max. I

meters

and

28 27

VCC

I/O

CMOS Programmable Electrically Erasable Logic Device

functionally

I/CLK

) power-down mode makes the

I/O

G ND

I/CLK

G ND

PCMCIA

similar

TSSOP

SOIC

PEEL™ 22LV10AZ-25 / I-35

VCC

I/O

modems.

VCC

ICT's

EE-

The differences between the PEEL22LV10AZ and

PEEL22CV10A include the addition of programmable

clock polarity, p-term clock, and Schmitt trigger input

buffers on all inputs, including the clock. Schmitt trigger

inputs allow direct input of slow signals such as

biomedical and sine waves or clocks. Like the

PEEL22CV10A, the PEEL22LV10AZ is a pin and

JEDEC compatible, logical superset of the industry

standard

PEEL22LV10AZ

features that allow more logic to be incorporated into

the design. The PEEL22LV10AZ architecture allows it

to replace over twenty standard 24-pin DIP, SOIC,

TSSOP

Figure 2 - Block Diagram

I/CLK

Architectural Flexibility

- Enhanced architecture fits in more logic

- 133 product terms x 44 input AND array

- 12 inputs and 10 I/O pins

- 12 possible macrocell configurations

- Asynchronous clear, synchronous preset

- Independent output enables

- Programmable clock; pin 1 or p-term

- Programmable clock polarity

- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC

- Schmitt triggers on clock and data inputs

Schmitt Trigger Inputs

- Eliminates external Schmitt trigger devices

- Ideal for encoder designs

133 Terms

PAL22V10

44 Inp uts

PEEL

ARRAY

"AND"

T M

and

provides

CLK MUX (O ptiona l)

O E

MACRO

Commercial/Industrial

CEL L

SPLD

PLCC

additional

SP = SYNCHRONO US PRESET

AC = ASYNCHRONO US CLEAR

O E = O UTPUT ENABLE

Figure

04-02-037D

architectural

packages.

The

I/O

Related parts for PEEL22LV10AZTI-25

PEEL22LV10AZTI-25 Summary of contents

Page 1

CMOS Programmable Electrically Erasable Logic Device Features Low Voltage, Ultra Low Power Operation - Vcc = 2 Icc = 5 µA (typical) at standby - Icc = 1.5 mA (typical MHz - Meets JEDEC ...

Page 2

I/CLK (9) 110 I* 111 (10) 121 I* 124 (11) 130 ...

Function Description The PEEL22LV10AZ implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase ...

Page 4

Programmable I/O Macrocell The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure independently lets you to tailor the configuration of the PEEL22LV10AZ to the precise requirements of your design. Macrocell Architecture ...

Page 5

Programmable Clock Options (see Table 1) A unique feature of the PEEL22LV10AZ programmable clock multiplexer that allows the user to select true or complement forms of either input pin or product-term clock sources. Operates in both 3 Volt and 3.3 ...

Page 6

Figure 6 - Twelve Extended I/O Macrocell Configurations (see Table 1) Configuration # ...

Page 7

Table 3 - Absolute Maximum Ratings Symbol Parameter V Supply Voltage Voltage Applied to Any Pin Output Current O T Storage Temperature ST T Lead Temperature LT Table 4 - Operating Range Symbol ...

Page 8

Table 6 - A.C. Electrical Characteristics 9 (Over the operating range ) Symbol Parameter 6 Input to non-registered output in continuous mode 6 t Input to output enable Input to output disable OD t ...

Page 9

... CMOS TTL Table 7 - Ordering Information Part Number PEEL22LV10AZP-25 PEEL22LV10AZPI-35 PEEL22LV10AZJ-25 PEEL22LV10AZJI-35 PEEL22LV10AZS-25 PEEL22LV10AZSI-35 PEEL22LV10AZT-25 PEEL22LV10AZTI-35 P ackag 24-pin Plactic 300 mil DIP J = 24-pin Plastic (J) Leaded Chip Carrier (PLCC 24-pin SOIC 300 mil Gullwing T = 24-pin TSSOP 170 mil 3.15V Thevenin Equivalent R1 Output ...

Page 10

Corporate Office 2123 Ringwood Avenue San Jose, CA 95131 TEL (408) 434-0678 FAX (408) 432-0815 ©2001 Integrated Circuit Technology Corp. ICT reserves the right to make changes in specifications at any time and without notice. The information furnished by ICT ...

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