MC54-74HC390 ONSEMI [ON Semiconductor], MC54-74HC390 Datasheet - Page 4

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MC54-74HC390

Manufacturer Part Number
MC54-74HC390
Description
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet
MOTOROLA
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
clock input to the
toggled by high–to–low transitions of the clock input.
CONTROL INPUTS
Reset (Pins 2, 14)
counting, resets the internal flip–flops, and forces Q A through
Q D low.
MC54/74HC390
Clock A is the clock input to the
Asynchronous reset. A high at the Reset input prevents
CLOCK
Q
10%
10%
50%
90%
90%
50%
10%
5 counter. The internal flip–flops are
t f
t w
t PLH
Figure 1.
t TLH
1/f max
t r
t PHL
2 counter; Clock B is the
t THL
* Includes all probe and jig capacitance
SWITCHING WAVEFORMS
DEVICE
UNDER
PIN DESCRIPTIONS
TEST
V CC
GND
TEST CIRCUIT
Figure 3.
OUTPUT
4
OUTPUTS
Q A (Pins 3, 13)
Q B , Q C , Q D (Pins 5, 6, 7, 9, 10, 11)
Q A is the least significant bit when the counter is connected
for BCD output as in Figure 4. Q B is the least significant bit
when the counter is operating in the bi–quinary mode as in
Figure 5.
CLOCK
RESET
TEST POINT
Output of the
Outputs of the
Q
C L *
t PHL
2 counter.
5 counter. Q D is the most significant bit.
Figure 2.
50%
t rec
50%
t w
50%
High–Speed CMOS Logic Data
DL129 — Rev 6
V CC
GND
V CC
GND

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