ISL6549 INTERSIL [Intersil Corporation], ISL6549 Datasheet
ISL6549
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ISL6549 Summary of contents
Page 1
... FB pins for undervoltage events. If either output drops below 75% of the nominal output level, both converters are shut off and go into retry mode. The ISL6549 is available SOIC package QSOP 4x4 QFN packages. Related Literature • Technical Brief TB363 Guidelines for Handling and ...
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... LGATE 5 10 LDO_DR PVCC5 LDO_FB 6 9 VCC5 GND 7 8 VCC12 Block Diagram VOLTAGE REFERENCE LDO_FB LDO_DR EA2 DIS FS_DIS GND 2 ISL6549 ISL6549 (QFN) TOP VIEW COMP 1 12 METAL GND PAD LDO_DR 3 (BOTTOM LDO_FB VCC5 ...
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... C +V IN2 + C VIN2 Q3 V OUT2 + C OUT2 3 ISL6549 LINEAR Q3 CONTROLLER CONTROLLER ISL6549 VCC12 PVCC5 BP VCC5 BOOT C BP5 UGATE LDO_DR PHASE LGATE LDO_FB ISL6549 FB FS_DIS COMP PGND GND Q1 V OUT1 PWM + Q2 C BP12 + C VIN1 C BOOT Q1 L OUT Q2 V OUT1 + C OUT1 FN9168.2 September 22, 2006 ...
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... UGATE, LGATE and LDO_DR open; CC12 F = 620kHz OSC I UGATE, LGATE and LDO_DR open; CC5 F = 620kHz OSC I PVCC5 I PVCC5CL V ISL6549C; No external load PVCC5 ISL6549I; No external load VCC12 = 12V VCC12 = 12V VCC5 = 5V VCC5 = 5V F ISL6549C 45.3kΩ OSC FS_DIS ISL6549I 45.3kΩ FS_DIS θ θ ...
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... Guaranteed by design, not production tested. Exceeding the maximum current from PVCC5 may result in degraded performance and unsafe operation. 6. Guaranteed by design, not production tested. 5 ISL6549 SYMBOL TEST CONDITIONS DV OSC 620kHz SS OSC V ISL6549C; For Error Amp 1 and 2 REF ISL6549I; For Error Amp 1 and 10K 10pF L L GBWP R = 10K 10pF 10K 10pF L L ⎜ ...
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... This output pin drives the lower MOSFET gate from the internal 5V regulator. Connect it to the gate of the lower MOSFET via a short, low inductance trace. 6 ISL6549 the available external inverting input pin of the error amplifier. Connect the output of the switching regulator to this pin through a properly sized resistor divider, to set the output voltage ...
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... Initialization The ISL6549 automatically initializes upon application of input power (at the VCC12) pin. The ISL6549 creates its own PVCC5 and VCC5 supplies for internal use. The POR function continually monitors the input bias supply voltage at the VCC12 and VCC5 pins. The POR function initiates soft- start operation after both these supply voltages exceed their POR rising threshold voltages ...
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... If the switcher output is already pre-charged to a voltage when the regulator starts up, the ISL6549 will detect this condition (see Figure 3). The red trace shows the normal ramp, when the output starts at GND. The green trace shows the case when the output is pre-charged to a voltage less than the final output ...
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... Output Voltage Selection is INx The output voltage of the PWM converter can be programmed to any level between V However, even though the ISL6549 can run at near 100% will recover on OUTs duty cycle at zero load, additional voltage margin is required above V used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier (see Figure 7). A typical value for R1 may be 1.00kΩ ...
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... PVCC5 (nominally around 5.25V) will be the bootstrap supply. In the event that the UGATE is on for an extended period of time, the charge on the boot capacitor can start to sag, raising the R of the upper FET. The ISL6549 has a circuit that DS(ON) detects a long UGATE on-time (32 oscillator clock periods), 10 ...
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... – ISL6549 4. Calculate R3 such that F such that F times F Change the numerical factor to reflect desired placement C3 of this pole. Placement reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter ...
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... MODULATOR GAIN current. Given a sufficiently fast control loop design, the COMPENSATION GAIN ISL6549 will provide either 0% or 100% duty cycle in CLOSED LOOP GAIN OPEN LOOP E/A GAIN response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
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... DC load current. Several electrolytic capacitors may be needed. Bootstrap Capacitor Selection The boot diode is internal to the ISL6549, and uses PVCC5 to charge the external boot capacitor. The size of the bootstrap capacitor can be chosen by using the equations in Equation 12 ...
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... FETs. Optimizing the sum involves many trade-offs (for example, raising the voltage of the gate drivers 14 ISL6549 typically adds power to the IC side, but may reduce some power on the FET side). For low duty cycle applications (such as 12V in to 1.5V out), the upper FET is usually chosen for low ...
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... FB pin with vias tied straight to the ground plane as required. Then the switching components should be placed close to the ISL6549. Minimize the length of the connections between the input capacitors and the power switches by placing them IN nearby ...
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... Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 16 ISL6549 L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL A 0. 0.23 D 4.00 BSC D1 3.75 BSC D2 1.95 E 4.00 BSC E1 3.75 BSC E2 1. 0. θ ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 17 ISL6549 M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 ISL6549 M16.15A 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY) ...