ISL65426_07 INTERSIL [Intersil Corporation], ISL65426_07 Datasheet

no-image

ISL65426_07

Manufacturer Part Number
ISL65426_07
Description
6A Dual Synchronous Buck Regulator with Integrated MOSFETs
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
6A Dual Synchronous Buck Regulator
with Integrated MOSFETs
The ISL65426 is a high efficiency dual output monolithic
synchronous buck converter operating over an input
voltage range of 2.375V to 5.5V. This single chip power
solution provides two output voltages which are selectable
or externally adjustable from 1V to 80% of the supply
voltage while delivering up to 6A of total output current. The
two PWMs are synchronized 180
the RMS input current and ripple voltage.
The ISL65426 switches at a fixed frequency of 1MHz and
utilizes current-mode control with integrated compensation
to minimize the size and number of external components
and provide excellent transient response. The internal
synchronous power switches are optimized for good
thermal performance, high efficiency, and eliminate the
need for an external Schottky diode.
A unique power block architecture allows partitioning of six
1A capable blocks to support one of four configuration
options. One master power block is associated with each
synchronous converter channel. Four floating slave power
blocks allow the user to assign them to either channel.
Proper external configuration of the power blocks is verified
internally prior to soft-start initialization.
Independent enable inputs allow for synchronization or
sequencing soft-start intervals of the two converter
channels. A third enable input allows additional sequencing
for multi-input bias supply designs. Individual power good
indicators (PG1, PG2) signal when output voltage is within
regulation window.
The ISL65426 integrates protection for both synchronous
buck regulator channels. The fault conditions include
overcurrent, undervoltage, and IC thermal monitor.
High integration contained in a thin Quad Flat No-lead
(QFN) package makes the ISL65426 an ideal choice to
power many of today’s small form factor applications. A
single chip solution for large scale digital ICs, like field
programmable gate arrays (FPGA), requiring separate core
and I/O voltages.
®
1
°
out of phase reducing
Data Sheet
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• High Efficiency: Up to 95%
• Fixed Frequency: 1MHz
• Operates From 2.375V to 5.5V Supply
• ±1% Reference
• Flexible Output Voltage Options
• User-Partitioned Power Blocks
• Ultra-Compact DC/DC Converter Design
• PWMs Synchronized 180
• Independent Enable Inputs and System Enable
• Stable All Ceramic Solutions
• Excellent Dynamic Response
• Independent Output Digital Soft-Start
• Power Good Output Voltage Monitor
• Short-Circuit and Thermal-Overload Protection
• Overcurrent and Undervoltage Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• FPGA, CPLD, DSP, and CPU Core and I/O Voltages
• Low-Voltage, High-Density Distributed Power Systems
• Point-of-Load Regulation
• Distributed Power Systems
• Set-Top Boxes
Ordering Information
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
ISL65426HRZ* ISL65426 HRZ -10 to +100 50 Ld 5x10
ISL65426IRZA* ISL65426 IRZ -40 to +85 50 Ld 5x10
- Programmable 2-Bit VID Input
- Adjustable Output From 0.6V to 4.0V
- Xilinx Spartan III
- Altera Stratix
- Actel Fusion
NUMBER
February 21, 2007
Virtex 4
(Note)
PART
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
TM
All other trademarks mentioned are the property of their respective owners.
Copyright © Intersil Americas Inc. 2006-2007. All Rights Reserved
TM
MARKING
TM
,
PART
,
LatticeSC
Stratix II
TM
, Virtex II
°
Out of Phase
TM
TM
RANGE
,
TEMP.
TM
, LatticeEC
Cyclone
(°C)
,
Virtex II Pro
QFN
QFN
ISL65426
TM
PACKAGE
(Pb-free)
,
TM
Cyclone II
FN6340.2
TM
,
TM
L50.5x10
L50.5x10
DWG. #
PKG.

Related parts for ISL65426_07

ISL65426_07 Summary of contents

Page 1

Data Sheet 6A Dual Synchronous Buck Regulator with Integrated MOSFETs The ISL65426 is a high efficiency dual output monolithic synchronous buck converter operating over an input voltage range of 2.375V to 5.5V. This single chip power solution provides two ...

Page 2

Pinout ISL65426 (50 LD QFN) TOP VIEW PGND 1 PGND 2 PGND 3 PGND 4 5 LX1 LX1 6 7 PVIN1 PGND PVIN2 8 LX2 9 PGND 10 11 PGND 12 LX3 PVIN3 ...

Page 3

Typical Application Schematics 3.3V 22μ 1.2V 1μ 200μF FIGURE 1. TYPICAL APPLICATION FOR 3A:3A CONFIGURATION 3 ISL65426 SINGLE INPUT SUPPLY 3.3V 3.3V PVIN1 PVIN2 PVIN3 LX1 LX2 ISL65426 LX3 FB1 3.3V PVIN6 3.3V PVIN5 C4 22μF ...

Page 4

Typical Application Schematics 5.0V 22μ 1.5V 0.6μ 200μF FIGURE 2. TYPICAL APPLICATION FOR 4A:2A CONFIGURATION 4 ISL65426 (Continued) DUAL INPUT SUPPLY 3.3V 5.0V PVIN1 PVIN2 PVIN3 PVIN4 ISL65426 LX1 LX2 LX3 LX4 FB1 3.3V PVIN6 3.3V ...

Page 5

Typical Application Schematics 5. 22μF 22μF L1 1.0μH C2 330μF 2.5V 5A 31.6kΩ 10kΩ FIGURE 3. TYPICAL APPLICATION FOR 5A:1A CONFIGURATION 5 ISL65426 (Continued) 5.0V 5.0V PVIN1 PVIN2 PVIN3 PVIN4 PVIN6 ISL65426 LX1 LX2 LX3 LX4 LX6 FB1 ...

Page 6

Functional Block Diagram SOFT START FB1 V1SET1 OUTPUT VOLTAGE V1SET2 CONFIG PGOOD1 PWM REFERENCE 0.60V SOFT START FB2 V2SET1 OUTPUT VOLTAGE CONFIG V2SET2 6 ISL65426 EN2 EN VCC GND POWER-ON RESET (POR) SLOPE COMPENSATION PWM CONTROL EA GM LOGIC COMPENSATION ...

Page 7

Absolute Maximum Ratings VCC, PVINx, LXx . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +6V FBx, ENx, VxSETx, ISETx, PGOODx ...

Page 8

Electrical Specifications Recommended operating conditions unless otherwise noted. VCC = PVIN = 5.0V -10°C to +100°C for ISL65426HRZ and T A PARAMETER Maximum Output Current Peak Output Current Limit Upper Device r DS(ON) Lower Device r DS(ON) Efficiency ...

Page 9

Typical Performance Curves 100 3.3V 5. 0.1 1.0 2.0 OUTPUT LOAD (A) FIGURE 1.2V EFFICIENCY vs LOAD OUT1 100 90 80 5.5V 70 3.3V IN ...

Page 10

Typical Performance Curves 1.235 1.225 1.215 5.5V IN 1.205 1.195 1.185 2.5V IN 1.175 1.165 0.1 1.0 2.0 OUTPUT LOAD (A) FIGURE 10 1.2V REGULATION vs LOAD OUT1 1.545 1.535 1.525 1.515 1.505 1.495 1.485 2.5V IN 1.475 ...

Page 11

Typical Performance Curves 1.845 1.825 3.3V IN 2.5V IN 1.805 1.785 5.5V 1.765 IN 1.745 0.1 0.5 1.0 OUTPUT LOAD (A) FIGURE 16 1.8V REGULATION vs LOAD OUT2 2.565 2.545 2.525 2.505 2.485 2.465 2.445 2.425 0.1 0.5 ...

Page 12

Typical Performance Curves EN1 5V/DIV PG1 5V/DIV FIGURE 22. START- 1.2V (NO LOAD) OUT1 EN1 5V/DIV PG1 5V/DIV FIGURE 24. START- 1.2V (FULL LOAD) OUT1 EN2 5V/DIV PG2 5V/DIV FIGURE 26. START- 3.3V (NO ...

Page 13

Typical Performance Curves EN2 5V/DIV PG2 5V/DIV FIGURE 28. START- 3.3V (FULL-LOAD) OUT2 V RIPPLE 20mV/DIV OUT1 I 500mA/DIV OUT1 V RIPPLE 50mV/DIV OUT2 FIGURE 30 1.2V LOAD TRANSIENT OUT1 LX1 5V/DIV V 500mV/DIV OUT1 IL1 ...

Page 14

Typical Performance Curves FIGURE 34 PGND 1 PGND 2 PGND 3 PGND 4 5 LX1 6 LX1 7 PVIN1 PGND PVIN2 8 LX2 9 10 PGND 11 PGND 12 LX3 PVIN3 13 ...

Page 15

EN System enable for voltage monitoring with programmable hysteresis. This pin has a POR rising threshold of 0.6V. This enable is intended for applications where two or more input power supplies are used and bias rise time is an issue. ...

Page 16

Table 2. When Each pin is pulled to GND by an internal 10μA pull down, this default condition programs the output voltage to the lowest level. The pull down prevents situations where a pin could be left floating for ...

Page 17

10μA + 0.6V ENABLE R2 Once the voltage at the EN pin reaches the enable threshold, the 10μA current sink turns off. With the part enabled and the current sink off, the disable ...

Page 18

Undervoltage Protection Separate hysteretic comparators monitor the feedback pin (FB) of each converter channel. The feedback voltage is compared to a set undervoltage (UV) threshold based on the output voltage selected. Once one of the comparators trip, indicating a valid ...

Page 19

ESL ---- - + ESR dt The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔV . MAX Most capacitor solutions rely on a mixture of high ...

Page 20

Component Placement Determine the total implementation area and orient the critical switching components first. These include the controller, input and output capacitors, and the output inductors. Symmetry is very important in determining how available space is filled and depends on ...

Page 21

Thermal Management For maximum thermal performance in high current, high switching frequency applications, connecting the thermal PGND pad of the ISL65426 to the ground plane with multiple vias is recommended. This heat spreading allows the IC to achieve its full ...

Page 22

L50.5x10 50 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 7/06 5.00 A PIN 1 INDEX AREA A TOP VIEW 9.80 8.10 3.30 4.80 RECOMMENDED LAND PATTERN All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. ...

Related keywords