HX640 LATTICE [Lattice Semiconductor], HX640 Datasheet
HX640
Related parts for HX640
HX640 Summary of contents
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... Lattice Semiconductor Corporation. All rights reserved. www.latticesemi.com Figure 1: iCE40 HX-Series Family Architectural Features 200 µ kHz (Typical) I/O Bank 0 Programmable Interconnect NVCM I/O Bank 2 Nonvolatile Configuration Memory (NVCM) HX640 640 8 32K 1 120 Kb 1 200 µ Area mm Pitch mm Programmable I/O: Max I/O (LVDS) 7x7 0 ...
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HX-Series Ultra-Low Power mobileFPGA Ordering Information Figure 2 describes the iCE40HX ordering codes for all packaged components. See the separate DiePlus data sheets when ordering die-based products. See the separate iCE40 Pinout Excel files for package and pinout specifications. ...
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HX-Series Ultra-Low Power mobileFPGA Electrical Characteristics All parameter limits are specified under worst-case supply voltage, junction temperature, and processing conditions. Absolute Maximum Ratings Stresses beyond those listed under functional operation of the device at these or any other conditions ...
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HX-Series Ultra-Low Power mobileFPGA I/O Characteristics Symbol Description I Input pin leakage current l I Three-state I/O pin (Hi-Z) OZ leakage current C PIO pin input capacitance PIO C GBIN global buffer pin GBIN input capacitance R Internal PIO ...
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HX-Series Ultra-Low Power mobileFPGA Differential Inputs Input common mode voltage V IN_B 50% V IN_A Input common mode voltage: Differential input voltage: Table 6: VCCIO_3 (V) I/O Standard Min Nom Max LVDS 2.38 2.50 2.63 SubLVDS 1.71 1.80 1.89 ...
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HX-Series Ultra-Low Power mobileFPGA AC Timing Guidelines The following examples provide some guidelines of device performance. The actual performance depends on the specific application and how it is physically implemented in the iCE65P FPGA using the Lattice iCEcube2 software. ...
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HX-Series Ultra-Low Power mobileFPGA Programmable Input/Output (PIO) Block Table 9 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths shown in Figure 7 and Figure 8. iCEcube2 development software reports timing adjustments ...
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HX-Series Ultra-Low Power mobileFPGA RAM4K Block Table 10 provides timing information for the logic in a RAM4K block, which includes the paths shown in PAD GBUF GBIN Write Setup/Hold Time t PIO GBIN Minimum write data setup time on ...
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HX-Series Ultra-Low Power mobileFPGA Phase-Locked Loop (PLL) Block Table 11 provides timing information for the Phase-Locked Loop (PLL) block shown in Symbol From To Frequency Range F Input clock frequency range REF F Output clock frequency range (cannot exceed ...
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... Supported by some high-speed SPI serial Flash PROMs 0 0 Oscillator turned off by default after configuration to save power. Table 12 and the maximum configuration bitstream size from Device Default iCE40HX640 iCE40HX1K iCE40HX4K 230 iCE40HX8K 230 Table 14: General Configuration Timing Description Minimum CRESET_B Low pulse width required to restart ...
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... NOTE: The typical static current for I/O Banks and the SPI bank is less than the accuracy of the device tester. Power Estimator To estimate the power consumption for a specific application, please download and use the iCE40HX Power Estimator Spreadsheet our use the power estimator built into the iCEcube2 software. Lattice Semiconductor Corporation www.latticesemi.com/ iCE40HX640 iCE40HX1K VCC Typical Typical 1.2V ...
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HX-Series Ultra-Low Power mobileFPGA Revision History Version Date 1.31 30-MAR-2012 Updated 1.3 22-MAR-2012 Production Release Updated Notes on Updated values in 1.21 5-MAR-2012 Updated 1.2 13-FEB-2012 Updated company name 1.1 15-DEC-2011 Moved package specifications to iCE40 Pinout Excel files. ...