EDD1216AJTA5BE Elpida Memory, Inc., EDD1216AJTA5BE Datasheet
EDD1216AJTA5BE
Manufacturer Part Number
EDD1216AJTA5BE
Description
TSOP-66
Manufacturer
Elpida Memory, Inc.
Datasheet
1.EDD1216AJTA5BE.pdf
(52 pages)
Specifications of EDD1216AJTA5BE
Date_code
05+
Specifications
Document No. E0972E30 (Ver. 3.0)
Date Published July 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Density: 128M bits
Organization
Package: 66-pin plastic TSOP (II)
Power supply: VDD, VDDQ
Data rate: 400Mbps/333Mbps/266Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
/CAS Latency (CL): 2, 2.5, 3
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 4096 cycles/64ms
Operating ambient temperature range
2M words
Lead-free (RoHS compliant)
Sequential (2, 4, 8)
Interleave (2, 4, 8)
Average refresh period: 15.6 s
TA = 0 C to +70 C
16 bits
EDD1216AJTA (8M words 16 bits)
4 banks
128M bits DDR SDRAM
2.5V
0.2V
DATA SHEET
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Elpida Memory, Inc. 2006-2007
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