EDD5116AFTA5BE Elpida Memory, Inc., EDD5116AFTA5BE Datasheet

EDD5116AFTA5BE

Manufacturer Part Number

EDD5116AFTA5BE

Description

TSOP

Manufacturer

Elpida Memory, Inc.

Datasheet

1.EDD5116AFTA5BE.pdf (48 pages)

Specifications of EDD5116AFTA5BE

Date_code

07+

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Description

The EDD5108AFTA and the EDD5116AFTA are 512M

bits Double Data Rate (DDR) SDRAM organized as

16,777,216 words

words

write operations are performed at the cross points of

the CK and the /CK. This high-speed data transfer is

realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and write are available

for high speed and reliable data bus design. By setting

extended mode register, the on-chip Delay Locked

Loop (DLL) can be set enable or disable. They are

packaged in standard 66-pin plastic TSOP (II).

Features

Document No. E0741E20 (Ver. 2.0)

Date Published October 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Power supply: VDD ,VDDQ = 2.6V

Data rate: 400Mbps (max.)

Double Data Rate architecture; two data transfers per

clock cycle

Bi-directional data strobe (DQS) is transmitted

/received with data for capturing data at the receiver

Data inputs, outputs, and DM are synchronized with

DQS

4 internal banks for concurrent operation

DQS is edge aligned with data for READs; center

aligned with data for WRITEs

Differential clock inputs (CK and /CK)

DLL aligns DQ and DQS transitions with CK

transitions

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

Data mask (DM) for write data

Auto precharge option for each burst access

SSTL_2 compatible I/O

Programmable burst length (BL): 2, 4, 8

Programmable /CAS latency (CL): 3

Programmable output driver strength: normal/weak

Refresh cycles: 8192 refresh cycles/64ms

2 variations of refresh

TSOP (II) package with lead free solder (Sn-Bi)

7.8 s maximum average periodic refresh interval

Auto refresh

Self refresh

RoHS compliant

16 bits

EDD5116AFTA-5 (32M words 16 bits, DDR400)

EDD5108AFTA-5 (64M words 8 bits, DDR400)

4 banks, respectively. Read and

8 bits

512M bits DDR SDRAM

4 banks and 8,388,608

0.1V

DATA SHEET

Pin Configurations

/xxx indicates active low signal.

A10(AP)

A0 to A12

BA0, BA1

DQ0 to DQ15

DQS, LDQS, UDQS

/CS

/RAS

/CAS

/WE

DM, LDM, UDM

/CK

CKE

VREF

VDD

VSS

VDDQ

VSSQ

VDDQ

VSSQ

/CAS

/RAS

VDD

DQ0

DQ1

DQ2

DQ3

VDD

/WE

BA0

BA1

/CS

A10(AP)

VDDQ

VSSQ

LDQS

/CAS

/RAS

VDD

LDM

VDD

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

/WE

BA0

BA1

/CS

66-pin Plastic TSOP(II)

Address input

Bank select address

Data-input/output

Input and output data strobe

Chip select

Row address strobe command

Column address strobe command

Write enable

Input mask

Clock input

Differential clock input

Clock enable

Input reference voltage

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

(Top view)

X 16

X 8

Elpida Memory, Inc. 2005

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSSQ

UDQS

VREF

VSS

UDM

/CK

CKE

A12

A11

VSS

DQ7

VSSQ

DQ6

VDDQ

DQ5

VSSQ

DQ4

VDDQ

VSSQ

DQS

VREF

VSS

/CK

CKE

A12

A11

VSS

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