EM638165TS7G Etron Technology Inc., EM638165TS7G Datasheet

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EM638165TS7G

Manufacturer Part Number
EM638165TS7G
Description
TSOP54
Manufacturer
Etron Technology Inc.
Datasheet

Specifications of EM638165TS7G

Date_code
07+
Features
Overview
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
system can choose the most suitable modes to
maximize its performance. These devices are well
suited
bandwidth
performance PC applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Fast access time from clock: 5/6/6/6/7 ns
Fast clock rate: 166/143/133/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
The EM638165 SDRAM is a high-speed CMOS
The EM638165 provides for programmable Read
By having a programmable mode register, the
for
and
applications
0.3V power supply
particularly
requiring
well
FAX: (886)-3-5778671
suited
4Mega x 16 Synchronous DRAM (SDRAM)
high
to
memory
high
Key Specifications
t
t
t
t
Ordering Information
CK3
AC3
RAS
RC
EM638165TS-6
EM638165TS-7
EM638165TS-7.5
EM638165TS-8
EM638165TS-10
A10/AP
Part Number
VDDQ
VDDQ
LDQM
VSSQ
VSSQ
CAS#
RAS#
WE#
Clock Cycle time(min.)
Access time from CLK(max.)
Row Active time(max.)
Row Cycle time(min.)
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDD
VDD
CS#
BA0
BA1
Pin Assignment (Top View)
A0
A1
A2
A3
EM638165
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Preliminary (Rev 0.6, 2/2001)
Frequency
166MHz
143MHz
133MHz
125MHz
100MHz
EM638165
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
42/45/45/48/50 ns
60/63/68/70/80 ns
-
5/5.4/5.4/6/7 ns
6/7/7.5/8/10 ns
6/7/7.5/8/10
Package
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II

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