EDE1116ACSE-6E-E Elpida Memory, Inc., EDE1116ACSE-6E-E Datasheet

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EDE1116ACSE-6E-E

Manufacturer Part Number
EDE1116ACSE-6E-E
Description
Manufacturer
Elpida Memory, Inc.
Datasheet

Specifications of EDE1116ACSE-6E-E

Package
BGA
Date_code
08+

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Specifications
Document No. E0975E50 (Ver.5.0)
Date Published May 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Density: 1G bits
Organization
Package
Power supply: VDD, VDDQ
Data rate
1KB page size (EDE1104/1108ACSE)
2KB page size (EDE1116ACSE)
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
/CAS Latency (CL): 3, 4, 5, 6
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Operating case temperature range
32M words
16M words
8M words
60-ball FBGA (EDE1104/1108ACSE)
84-ball FBGA (EDE1116ACSE)
Lead-free (RoHS compliant)
800Mbps/667Mbps/533Mbps (max.)
Row address: A0 to A13
Column address: A0 to A9, A11 (EDE1104ACSE)
Row address: A0 to A12
Column address: A0 to A9
Sequential (4, 8)
Interleave (4, 8)
Average refresh period
7.8 s at 0 C
3.9 s at 85 C
TC = 0 C to +95 C
16 bits
4 bits
8 bits
TC
A0 to A9 (EDE1108ACSE)
TC
EDE1104ACSE (256M words 4 bits)
EDE1108ACSE (128M words 8 bits)
EDE1116ACSE (64M words 16 bits)
8 banks (EDE1104ACSE)
8 banks (EDE1108ACSE)
8 banks (EDE1116ACSE)
85 C
95 C
1G bits DDR2 SDRAM
1.8V
0.1V
DATA SHEET
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
organization compatible to
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Elpida Memory, Inc. 2006-2008
4 organization
8

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