EM635327TQ-10 Etron Technology Inc., EM635327TQ-10 Datasheet

EM635327TQ-10

Manufacturer Part Number

EM635327TQ-10

Description

Manufacturer

Etron Technology Inc.

Datasheet

1.EM635327TQ-10.pdf (78 pages)

Specifications of EM635327TQ-10

Case

QFP

Date_code

98+

Current page: 1 of 78
Download datasheet (2Mb)

Features

Overview

CMOS synchronous graphics DRAM containing 8

Mbits. It is internally configured as a dual 128K x

32 DRAM with a synchronous interface (all signals

are registered on the positive edge of the clock

signal, CLK). Each of the 128K x 32 bit banks is

organized as 512 rows by 256 columns by 32 bits.

Read and write accesses to the SGRAM are burst

oriented; accesses start at a selected location and

continue for a programmed number of locations in

a programmed sequence. Accesses begin with the

registration of a BankActivate command which is

then followed by a Read or Write command.

Read or Write burst lengths of 1, 2, 4, 8, or full

Etron Technology, Inc.

1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C

TEL: (886)-3-5782345 FAX: (886)-3-5779001

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

Fast access time from clock: 6.5/7.0/7.5/8.5ns

Fast clock rate: 125/110/100/83MHz

Fully synchronous operation

Internal pipelined architecture

Dual internal banks(128K x 32-bit x 2-bank)

Programmable Mode and Special Mode registers

- CAS# Latency: 1, 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst-Read-Single-Write

- Load Color or Mask register

Burst stop function

Individual byte controlled by DQM0-3

Block write and write-per-bit capability

Auto Refresh and Self Refresh

1024 refresh cycles/16ms

Single +3.3V 0.3V power supply

Interface: LVTTL compatible

JEDEC 100-pin Plastic package

- QFP (body thickness = 2.8mm)

- TQFP1.4 (body thickness = 1.4mm)

256K x 32 High Speed Synchronous Graphics DRAM(SGRAM)

The EM635327 SGRAM is a high-speed

The EM635327 provides for programmable

Key Specifications

Ordering Information

page, with a burst termination option. An auto

precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end

of the burst sequence. The refresh functions,

either Auto or Self Refresh are easy to use. In

addition, the EM635327 features the write-per-bit

and the masked block write functions.

and special mode register, the system can choose

the most

performance. These devices are well suited for

applications requiring high memory bandwidth,

and

functions result in a device particularly well suited

to high performance graphics applications.

CK3

RAS

AC1

AC3

EM635327Q-12

EM635327R-12

EM635327TQ-12

EM636327TR-12

EM635327Q-10

EM635327R-10

EM635327TQ-10

EM635327TR-10

EM635327Q-9

EM635327R-9

EM635327TQ-9

EM635327TR-9

EM635327Q-8

EM635327R-8

EM635327TQ-8

EM635327TR-8

Part Number

Clock Cycle time(min.)

Row Active time(max.)

Access time from Read command

Access time from CLK(max.)

Row Cycle time(min.)

when

By having a programmable mode register

EM635327

suitable

combined

Frequency

100MHz

110MHz

125MHz

83MHz

modes to

with

Preliminary (10/'97)

EM635327

TQFP1.4(Forward)

TQFP1.4(Reverse)

TQFP1.4(Forward)

TQFP1.4(Reverse)

TQFP1.4(Forward)

TQFP1.4(Reverse)

TQFP1.4(Forward)

TQFP1.4(Reverse)

special

QFP(Reverse)

QFP(Forward)

maximize

Package

6.5/7.0/7.5/8.5ns

22/24.5/27/32ns

72/81/90/108ns

48/54/60/72ns

- 8/9/10/12

8/9/10/12ns

graphics

its

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