QL16X24B-2PF144I QuickLogic Corp, QL16X24B-2PF144I Datasheet

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QL16X24B-2PF144I

Manufacturer Part Number
QL16X24B-2PF144I
Description
Manufacturer
QuickLogic Corp
Datasheet

Specifications of QL16X24B-2PF144I

Case
TQFP/144
Date_code
99+
usable ASIC gates,
384 Logic Cells
Block Diagram
HIGHLIGHTS
122 I/O pins
QL16x24B
…4,000
pASIC
= Up to 114 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells
Low-Power, High-Output Drive – Standby current typically 2 mA.
A 16-bit counter operating at 100 MHz consumes less than 50 mA.
Minimum IOL of 12 mA and IOH of 8 mA
Low-Cost, Easy-to-Use Design Tools – Designs entered and
simulated using QuickLogic's new QuickWorks
environment, or with third-party CAE tools including Viewlogic,
Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place
and route on PC and workstation platforms using QuickLogic
software.
Very High Speed – ViaLink
antifuse technology, allows counter speeds over 150 MHz and logic
cell delays of under 2 ns.
High Usable Density
provides 4,000 usable ASIC gates (7,000 PLD gates) in 84-pin
PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA and 160-pin
CQFP packages.
4-21
Very-High-Speed CMOS FPGA
– A 16-by-24 array of 384 logic cells
metal-to-metal programmable–via
pASIC
QL16x24B
®
1 Family
development
Rev C
4

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