ASC7512 ETC2 [List of Unclassifed Manufacturers], ASC7512 Datasheet
ASC7512
Related parts for ASC7512
ASC7512 Summary of contents
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... CPU temperature under varying operational loads. To set fan speed, the aSC7512 has a pulse width modulation (PWM) output that is controlled by one of two temperature zones. Both high- and low-frequency PWM ranges are supported. The aSC7512 also includes a digital ...
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... MMBT3904 NPN transistor. Input for monitoring tachometer output of fan (default) or ALERT output selectable by configuration register 09h, bit 5. Fan speed control, Pulse Width Modulated www.andigilog.com aSC7512 SMBus Interface Limit Registers Limit Comparators Status Registers Fan T-min, T-range & T-Hyst Configuration Register ...
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... Parasitic components and/or ±5mA ESD protection circuitry are present on the aSC7512 ±20mA pins. Care should be taken not to forward bias the parasitic diode present on pins D+ and D-. Doing so by See (Note 3) more than 50mV may corrupt temperature measurements ...
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... 85°C; all other limits over MIN is the junction temperature of aSC7512 Conditions Converting, Interface and Fans Inactive, Peak Current Converting, Interface and Fans inactive, Average Current - 40°C ≤ T ≤ +100°C, A ≤ ...
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... ° 400pF -3mA All Digital Inputs www.andigilog.com aSC7512 = T A Min Typ Max Units (max) 65535 90 kHz 0.7 sec(max) 1. 22.5 kHz 30 kHz 0 to %(max) 100 0.3906 %/count 0 ms 4000 ms ...
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... These specifications are guaranteed only for the test conditions listed. 6. The accuracy of the aSC7512 is guaranteed when using the thermal diode of a processor or any thermal diode with a non-ideality of 1.008 and internal series resistance of 3.52Ω. When using a 2N3904 type transistor as a thermal diode the error band will be typically shifted depending on transistor characteristics. 7. Accuracy (expressed in ° ...
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... This register’s content is automatically set to the value of the first byte following the R/ W bit being set to 0. After the aSC7512 sends an ACK in response to receiving the address and R/ W bit, the master device must transmit an appropriate 8-bit address pointer value as explained in the Registers section of this data sheet ...
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... It is important to note that if the repeat start condition does not occur, the aSC7512 will assume that a write is taking place, and the selected register will be overwritten by the upcoming data on the data bus ...
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... ACK NACK from from Register Data Byte aSC7512 Master ACK NACK from from aSC7512 SMBus Address aSC7512 Master Figure 6 SMBus Alert Response - 9 - www.andigilog.com aSC7512 Stop by Master Stop by Master August 2006 - 70A05003 ...
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... Andigilog, Inc. 2006 The ALERT pin will remain low until the status bits have been reset and an Alert Response has been issued by the master and responded by the aSC7512. This flow is described below. The user may mask-out or disable the ALERT signal pin should it be necessary to prevent a processor interrupt ...
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... Meas Meas Meas Enable Blank1 Blank 0 Dwell VER2 VER1 VER0 STP3 RES RES RES OVRID - 11 - www.andigilog.com aSC7512 De- Bit 0 fault Bit 2 Bit 1 (LSB) Value (hex) ROPEN RES RES RES 00 08 CONV2 CONV1 CONV0 ...
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... ZN2-2 ZN2-1 ZN2-0 RES H1-2 H1-1 H1-0 H2-3 RES RES RES RES - 12 - www.andigilog.com aSC7512 De- Bit 0 fault Bit 2 Bit 1 (LSB) Value (hex) RES RES RES 00 FAN RES RES ...
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... Bit 7 Bit 6 Bit 5 Bit 4 (MSB) Alert Run/ Alert/ RES Mask Stop Tach CONV7 CONV6 CONV5 CONV4 - 13 - www.andigilog.com aSC7512 Bit 0 Bit 3 Bit 2 Bit 1 (LSB Low Byte Ignore XX XXXX ...
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... These configuration register settings apply to measurements and alerts reported in registers 25h-10h and 26h-15h temperature readings (10-Bit 2’s complement reporting). One-shot Measurement register address 0Fh initiates a temperature measurement when aSC7512 is in Stop mode and returns to that mode after both temperature measurements are complete. ...
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... R Alert Status The Alert Status Register is a read-only register for reporting the state of the aSC7512’s alarms read-only register located at 02h. When any high or low Zone 1 (remote) limits or high or low Zone 2 (local) limits are exceeded, bits 3 through 6 are set accordingly and the ALERT pin 6 will be driven low. If the remote sensor is open-circuit, bit 2 will be set and the ALERT will be asserted. Reading the status register will re-set these flags if the alerted condition has been removed, however, the ALERT pin will remain asserted until the master has serviced the SMBus alert. This register is read-only – ...
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... The register will hold a set bit(s) until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the aSC7512 after it is read by software, if the fault condition no longer exists. Once set, the Interrupt Status Register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists. This register is read-only – ...
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... When the LSByte of the aSC7512 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. At the end of the MSByte read the Fan Tachometer Reading registers are updated. During spin-up, the PWM duty cycle reported is 0% ...
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... When high, forces the PWM to stay high for the duration of a tach measurement for a 3-wire fan. This will result in R/W 0 increasing the PWM on-time percentage vs. the value in the PWM register. R/W 0 Suspends the 90KHz clock for power savings when high www.andigilog.com aSC7512 Description August 2006 - 70A05003 ...
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... Auto Fan Control Operating Mode The aSC7512 includes the circuitry for automatic fan control. In Auto Fan Mode, the aSC7512 will automatically adjust the PWM duty cycle of the PWM output. PWM outputs are assigned to a thermal zone based on the fan configuration registers. ...
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... START bit (bit 0), in the Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting the START bit to 1, the aSC7512 will operate using the values that were set by the BIOS in the fan control limit and parameter registers (address in the range 5Ch through 6Dh). ...
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... The PWM duty cycle will be 100% at (Fan Temp Limit + Range). PWM frequency - FRQ[3:0] and HLFRQ The PWM frequency bits [3:0] determine the PWM frequency for the fan. The aSC7512 has high and low frequency ranges for the PWM outputs that are controlled by the HLFRQ bit. ...
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... Once this bit is set, limit and parameter registers become read-only and will 0 remain locked until the device is powered off. This register bit becomes read-only once it is set. The aSC7512 sets this bit automatically after the part is fully powered up, has 0 completed the power-up-reset process, and after all A/D converters are properly functioning. ...
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... Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote - and Remote + inputs exceeds the Zone 1 High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature limits in these registers are represented as 8 bit 2’ ...
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... CPU Cooler 0 Memory Controller 0 Chassis Front 1 Chassis Rear 1 Table 14 Fan Location Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (MSB) ZON2 ZON1 ZON0 INV RES - 24 - www.andigilog.com aSC7512 Bit 3 Bit 2 Bit 1 Bit 0 (LSB Bit Bit 2 Bit 1 Bit 0 Default ...
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... If the Remote pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the aSC7512. Fan speed algorithm has two phases of filtering on temperature zone readings. First, a “No-Spike” value is created from the current temperature and three previous readings. This is an average of the two remaining values when the high and low values are removed ...
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... If these spikes are not filtered, the CPU fan (if connected to aSC7512) may turn on prematurely or produce unpleasant noise. For this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled. Individual system characteristics will determine how large this coefficient should be. ...
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... Two’s Complement - 27 - www.andigilog.com aSC7512 Bit 2 Bit 1 Bit 0 Default (LSB) Value Hex Bit 2 Bit 1 Bit 0 ...
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... Two’s Complement Bit 6 Bit 5 Bit 4 Bit 3 H1-2 H1-1 H1-0 H2-3 Temperature Zone Hysteresis Hn-[3:0] 0°C 0000 1°C 0001 4°C (default) 0100 10°C 1010 15°C 1111 - 28 - www.andigilog.com aSC7512 Bit 2 Bit 1 Bit 0 Default (LSB) Value 1111 1111 1101 0100 0010 1001 0000 1110 ...
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... Version/Stepping The four least significant bits of the Version/Stepping register [3:0] contain the current stepping of the aSC7512 silicon. The four most significant bits [7:4] reflect the aSC7512 base device number when set to a value of 0110b. For the aSC7512, this register will read 01101000b (62h). ...
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... Applications Information Remote Diodes The aSC7512 is designed to work with a variety of remote sensors in the form of the substrate thermal diode of a CPU or graphics controller or a diode-connected transistor. Actual diodes are not suited for these measurements. There is some variation in the performance of these diodes, described in terms of its departure from the ideal diode equation ...
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... Series Resistance Any external series resistance in the connections from the aSC7512 to the CPU pins should be accounted for in interpreting the results of a measurement. The impact of series resistance on the measured temperature is a result of measurement currents developing offset voltages that add to the diode voltage. ...
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... Optional connection to off-board SMBus clients Application Diagrams The aSC7512 may be easily adapted to two-, three wire fans for precise, wider-range fan speed control when compared to variable DC drive. Pin 6 may optionally be used as ALERT , pulled up to 3.3V with a 10K resistor to warn the system of an extreme condition needing immediate attention in any fan configuration ...
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... BSC 4.80mm (min) 4.98mm (max) 1.37mm (min) 1.57mm (max) 0.36mm (min) 0.46mm (max) α 0° (min) 8° (max www.andigilog.com aSC7512 7° β Detail 0.19mm (min) A 0.25mm (max) 0.41mm (min) 1.27mm (max) Detail A 0.25mm (min) 0.50mm (max) x 45° August 2006 - 70A05003 ...
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... Detail B α 0° (min) γ 6° (max) 0° (min) 0.40mm (min) 6° (max) ...
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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Andigilog, Inc. 8380 S. Kyrene Rd., Suite 101 Tempe, Arizona 85284 Tel: (480) 940-6200 Fax: (480) 940-4255 © Andigilog, Inc. 2006 - 35 - www.andigilog.com aSC7512 August 2006 - 70A05003 ...