W49F002U-70B WINBOND [Winbond], W49F002U-70B Datasheet

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W49F002U-70B

Manufacturer Part Number
W49F002U-70B
Description
256K X 8 CMOS FLASH MEMORY
Manufacturer
WINBOND [Winbond]
Datasheet
GENERAL DESCRIPTION
The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
not required. The unique cell architecture of the W49F002U results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
Fast Program operation:
Fast Erase operation: 100 mS (typ.)
Fast Read access time: 70/90/120 nS
Endurance: 10K cycles (typ.)
Ten-year data retention
Hardware data protection
One 16K byte Boot Block with Lockout
protection
Two 8K byte Parameter Blocks
5-volt Read
5-volt Erase
5-volt Program
Byte-by-Byte programming: 35 S (typ.)
256K
- 1 -
8 CMOS FLASH MEMORY
Two Main Memory Blocks (96K, 128K) Bytes
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 A (typ.)
Automatic program and erase timing with
internal V
End of program or erase detection
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP and 32-pin
TSOP and 32-pin-PLCC
Toggle bit
Data polling
PP
generation
Publication Release Date: April 2000
W49F002U
8 bits. The
Revision A2
PP
is

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W49F002U-70B Summary of contents

Page 1

... The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V not required. The unique cell architecture of the W49F002U results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products) ...

Page 2

... CE DQ2 23 DQ1 22 21 DQ0 GND - 2 - W49F002U OUTPUT CONTROL BUFFER BOOT BLOCK 16K BYTES PARAMETER BLOCK1 DECODER 8K BYTES PARAMETER BLOCK2 8K BYTES MAIN MEMORY BLOCK1 96K BYTES MAIN MEMORY BLOCK2 128K BYTES PIN NAME Reset Address Inputs ...

Page 3

... FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F002U is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed the output control and is used to gate data from the output pins ...

Page 4

... BP be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49F002U is also hardware protected in the following ways: (1) Noise/Glitch Protection pulse of less than duration will not initiate a write cycle. (2) V Power Up/Down Detection: The programming operation is inhibited when ...

Page 5

... Write Status Detection 6 In addition to data polling, the W49F002U provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop ...

Page 6

... CYCLE OUT 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 AA 2AAA 55 5555 A0 A 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 AA 2AAA 55 5555 90 5555 AA 2AAA 55 5555 F0 XXXX W49F002U 4TH 5TH 6TH CYCLE CYCLE CYCLE 5555 10 ( ...

Page 7

... Programmed-address Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmed- address Pause T BP Exit Publication Release Date: April 2000 - 7 - W49F002U DATA AAH 55H A0H Programmed-data Revision A2 ...

Page 8

... Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause T EC Exit - 8 - W49F002U DATA AAH 55H 80H AAH 55H 10H ...

Page 9

... Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA* Pause T EC Exit Publication Release Date: April 2000 - 9 - W49F002U DATA AAH 55H 80H AAH 55H 30H Revision A2 ...

Page 10

... Mode (3) (2) Read address = 0000 data = DA (2) Read address = 0001 (4) Read address = 0002 data =in DQ0= "1" / "0" ; device code is read for W49F002U SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT(6) DATA 5555H AAH 2AAAH 55H 5555H F0H Pause 10 S ...

Page 11

... Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause T BP Exit Publication Release Date: April 2000 - 11 - W49F002U DATA AAH 55H 80H AAH 55H 40H Revision A2 ...

Page 12

... DQs open IH Other inputs = -0.3V, all DQs open DD Other inputs = V -0.3V/GND GND GND to V OUT 2 -0 W49F002U RATING UNIT -0 +70 C -65 to +150 -0.5 to 12.5 V LIMITS UNIT MIN. TYP. MAX ...

Page 13

... MHz PARAMETER I/O Pin Capacitance Input Capacitance AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels SYMBOL T . READ WRITE PU SYMBOL CONDITIONS I W49F002U TYPICAL UNIT 100 MAX. UNIT CONDITIONS Publication Release Date: April 2000 Revision A2 ...

Page 14

... Data Setup Time Data Hold Time Byte Programming Time Erase Cycle Time Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is V SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT MIN. MAX. MIN ...

Page 15

... OE to Data Polling Output Delay Data Polling Output Delay OE to Toggle Bit Output Delay CE to Toggle Bit Output Delay TIMING WAVEFORMS Read Cycle Timing Diagram Address A17 High-Z DQ7-0 SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT MIN. MAX. MIN OEP - CEP - 35 ...

Page 16

... Controlled Command Write Cycle Timing Diagram WE Address A17 DQ7-0 Controlled Command Write Cycle Timing Diagram CE Address A17 DQ7 OES T WP Data Valid OES T DS High Z Data Valid - 16 - W49F002U OEH T WPH CPH T OEH T DH ...

Page 17

... DQ7 Byte Program Cycle 2AAA 5555 5555 WPH T WP Byte 0 Byte 1 Byte CEP T OEH T OEP W49F002U Address Data- Internal Write Start Byte OES X X Publication Release Date: April 2000 Revision A2 ...

Page 18

... Boot Block Lockout Enable Timing Diagram Address A17-0 5555 DQ7 SB0 T OEH Six byte code for Boot Block Lockout Feature Enable 5555 5555 2AAA 2AAA WPH SB2 SB3 SB4 SB1 - 18 - W49F002U T OES 5555 SB5 ...

Page 19

... Six-byte code for 5V-only software Main Memory Erase 5555 5555 2AAA 2AAA WPH SB0 SB2 SB3 SB4 SB1 - 19 - W49F002U 5555 Internal Erase starts SB5 Internal Erase starts SB5 Publication Release Date: April 2000 Revision A2 ...

Page 20

... ORDERING INFORMATION PART NO. ACCESS TIME (nS) W49F002U-70B 70 W49F002U-90B 90 W49F002U-12B 120 W49F002UT70B 70 W49F002UT90B 90 W49F002UT12B 120 W49F002UP70B 70 W49F002UP90B 90 W49F002UP12B 120 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure ...

Page 21

... Seating Plane Base Plane Seating Plane W49F002U Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.210 5.33 A 0.010 0. 0.150 0.155 0.160 3.81 3.94 4. 0.016 0.018 0.022 0.41 0.46 0. ...

Page 22

... Package Dimensions, continued 32-pin TSOP 0.10(0.004 W49F002U Dimension in Inches Dimension in mm Symbol Min. Nom. Min. Nom. Max. Max 1.20 0.047 0.002 0.006 0.05 0. 0.95 0.037 0.039 0.041 1.00 1. 0.007 0.008 0.17 0.20 0.23 0.009 c 0.005 ...

Page 23

... Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 - 23 - W49F002U DESCRIPTION Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U ...

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