K6T0808C1D-DB55 SAMSUNG [Samsung semiconductor], K6T0808C1D-DB55 Datasheet - Page 7

• Manufacturer Part Number: K6T0808C1D-DB55
• Description: 32Kx8 bit Low Power CMOS Static RAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

DATA RETENTION WAVE FORM
TIMING WAVEFORM OF WRITE CYCLE(1)
K6T0808C1D Family
Address
CS
WE
Data in
Data out
CS controlled
TIMING WAVEFORM OF WRITE CYCLE(2)
Address
CS
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
2. t
3. t
4. t
V
4.5V
2.2V
V
CS
GND
CC
DR
going low : A write end at the earliest transition among CS going high and WE going high, t
to the end of write.
CW
AS
WR
is measured from the CS going low to end of write.
is measured from the address valid to the beginning of write.
is measured from the end of write to the address change. t
Data Undefined
High-Z
t
t
AS(3)
SDR
t
AS(3)
(WE Controlled)
(CS Controlled)
t
WHZ
t
AW
WR
Data Retention Mode
t
applied in case a write ends as CS or WE going high.
CW(2)
t
WC
t
CS V
AW
t
t
WC
t
CW(2)
WP(1)
CC
t
WP(1)
- 0.2V
t
DW
Data Valid
t
DW
Data Valid
t
WR(4)
WP
is measured from the begining of write
t
t
DH
WR(4)
t
OW
t
DH
High-Z
t
RDR
CMOS SRAM
November 1997
Revision 1.0