K9F5608D0D SAMSUNG [Samsung semiconductor], K9F5608D0D Datasheet

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K9F5608D0D

Manufacturer Part Number
K9F5608D0D
Description
32M x 8 Bit NAND Flash Memory
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K9F5608R0D
K9F5608U0D
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
K9F5608D0D
K9F5608X0D
1
FLASH MEMORY

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K9F5608D0D Summary of contents

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... K9F5608R0D K9F5608U0D K9F5608D0D INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Document Title 32M x 8 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue 0.1 1. Leaded package devices are eliminated 0.2 1.0 1.1 1. LOCKPRE pin mode is eliminated Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. ...

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... K9F5608D0D-P 2.4 ~ 2.9V K9F5608D0D-J K9F5608U0D-P 2.7 ~ 3.6V K9F5608U0D-J K9F5608U0D-F FEATURES • Voltage Supply - 1.8V device(K9F5608R0D) : 1.65~1.95V - 2.65V device(K9F5608D0D) : 2.4~2.9V - 3.3V device(K9F5608U0D) : 2.7 ~ 3.6 V • Organization - Memory Cell Array -(32M + 1024K)bit x 8 bit - Data Register - (512 + 16)bit x 8bit • Automatic Program and Erase - Page Program -(512 + 16)Byte - Block Erase : - (16K + 512)Byte • ...

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... K9F5608R0D K9F5608U0D K9F5608D0D PIN CONFIGURATION (TSOP1) N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8° 0.45~0.75 0.018~0.030 K9F5608D(U)0D-PCB0/PIB0 ...

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... K9F5608R0D K9F5608U0D K9F5608D0D PIN CONFIGURATION (FBGA PACKAGE DIMENSIONS 63-Ball FBGA (measured in millimeters) Top View 9.00 ±0.10 #A1 K9F5608X0D-JCB0/JIB0 Top View N.C N.C N.C N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE ...

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... K9F5608R0D K9F5608U0D K9F5608D0D PIN CONFIGURATION (WSOP1) N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 ...

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... K9F5608R0D K9F5608U0D K9F5608D0D PIN DESCRIPTION Pin NAME DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Figure 1-1. K9F5608X0D FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F5608X0D ARRAY ORGANIZATION 64K Pages 1st half Page Register ...

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... K9F5608R0D K9F5608U0D K9F5608D0D PRODUCT INTRODUCTION The K9F5608X0D is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations.The memory array is made cells that are serially connected to form a NAND structure ...

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... IN/OUT 4.6 CCQ -10 to +125 T BIAS -40 to +125 T -65 to +150 STG Ios +0.3V which, during transitions, may overshoot 70°C, K9F5608X0D-XIB0 T =-40 to 85° K9F5608D0D(2.65V) Typ. Max Min Typ. Max 1.8 1.95 2.4 2.65 2.9 1.8 1.95 2.4 2.65 2 FLASH MEMORY Rating Unit V ° ...

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... Output High Voltage V K9F5608D0D :I OH Level K9F5608U0D :I K9F5608R0D :I Output Low Voltage V K9F5608D0D :I OL Level K9F5608U0D :I K9F5608R0D :V Output Low Current(R/B) I (R/B) K9F5608D0D :V OL K9F5608U0D :V NOTE : V can undershoot to -0.4V and V can overshoot (Recommended operating conditions otherwise noted.) Test Conditions 1.8V Min Typ Max Min Typ ...

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... Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space TEST CONDITION (K9F5608X0D-XCB0 :TA=0 to 70°C, K9F5608X0D-XIB0:TA=-40 to 85°C K9F5608R0D : Vcc=1.65V~1.95V , K9F5608D0D : Vcc=2.4V~2.9V , K9F5608U0D : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times ...

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... K9F5608R0D K9F5608U0D K9F5608D0D PROGRAM/ERASE CHARACTERISTICS Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT Parameter Symbol CLE setup Time t CLS CLE Hold Time t CLH CE setup Time Hold Time t CH ...

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... K9F5608U0D- Last RE High to Busy(at sequential read) P High to Ready(in case of interception K9F5608D0D-- CE High Hold Time(at the last serial read) P only NOTE: 1. K9F5608R0D tREA = 35ns reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 3. The time to Ready depends on the value of the pull-up resistor tied R/B pin. ...

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... K9F5608R0D K9F5608U0D K9F5608D0D NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...

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... K9F5608R0D K9F5608U0D K9F5608D0D NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...

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... K9F5608R0D K9F5608U0D K9F5608D0D NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Pointer Operation of K9F5608X0D(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...

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... Figure 6. Program Operation with CE don’t-care. CLE CE WE ALE I/Ox 80h Start Add.(3Cycle Figure 7. Read Operation with CE don’t-care. CLE On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y ALE R/B WE I/Ox 00h Start Add.(3Cycle) CE don’t-care Data Input I/O ~ ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Device K9F5608X0D(X8 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. I/O8~15 are used only for data bus. Command Latch Cycle CLE t CLS ALS ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE I/Ox I/O I/ CLH ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 Sequential Out Cycle after Read CE t REA RE I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested ...

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... Address Address R 528 , Read CMD = 00h or 01h t CLR t CLH CEA t WHR1 70h On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P CE must be held low during Dout N Dout N+1 Dout N+2 A17~A24 Busy NOTES : 1) is only valid 22 FLASH MEMORY t CHZ t ...

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... Valid Address & K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P CE must be held low during Dout N+2 Dout N Dout N+1 Row Add2 Busy On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P CE must be held low during Dout Row Add2 Selected Row ~A are Don ′t care 4 7 ...

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... R/B M Page Program Operation CLE ALE RE N Address I/Ox 80h Row Add1 Col. Add Sequential Data Column Page(Row) Input Command Address Address R/B (only for On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P Dout Dout Dout Dout N N+1 N+2 527 Ready Busy M+1 N Output ADL Din Din Din 10h ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Copy-Back Program Operation CLE ALE RE I/Ox 00h Col. Add Row Add1 Row Add2 Column Page(Row) Address Address R/B Block Erase Operation (Erase One Block) CLE ALE RE I/Ox 60h A9~A16 A17~A24 Page(Row) Address R/B Auto Block Erase Setup Command ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Manufacture & Device ID Read Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle REA 00h ECh Maker Code Device K9F5608R0D K9F5608D0D K9F5608U0D 26 FLASH MEMORY Device Code* Device Code Device Code* 35h 75h 75h ...

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... NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. ~A are ignored . The Read1 command is needed to move the pointer back K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P CE must be held low during Data Output(Sequential) (00h Command) 1) ...

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... Start Add.(3Cycle) 00h 01h & (00h Command) 1st half array Block Data Field On K9F5608U0D_Y,P,V,F or K9F5608D0D_Y,P CE must be held low during Data Output(Sequential) Main array Data Field Spare Field (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y Data Output ...

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... Figure 9-1. Sequential Row Read2 Operation R/B I/Ox Start Add.(3Cycle) 50h & ′ Don t Care) (only for K9F5608U0D_Y,P,V,F or K9F5608D0D_Y Data Output Data Output 1st 24 1st Block Nth Data Field Spare Field 29 FLASH MEMORY ) t R Data Output 2nd ...

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... K9F5608R0D K9F5608U0D K9F5608D0D PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block ...

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... K9F5608R0D K9F5608U0D K9F5608D0D BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...

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... Figure 14. RESET Operation R/B I/Ox FFh Table5. Device Status Operation Mode t CEA WHR1 REA ECh Maker code Device K9F5608R0D K9F5608D0D K9F5608U0D t RST After Power-up Read 1 Waiting for next command 32 FLASH MEMORY Device Code* Device code Device Code* 35h 75h 75h After Reset ...

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... K9F5608R0D K9F5608U0D K9F5608D0D READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...

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... K9F5608R0D K9F5608U0D K9F5608D0D 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance V (Max Rp(min, 1.8V part (Max Rp(min, 2.65V part (Max Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. L Rp(max) is determined by maximum permissible limit of tr ° ...

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... K9F5608R0D K9F5608U0D K9F5608D0D Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 16 ...

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