H5PS1G63EFR HYNIX [Hynix Semiconductor], H5PS1G63EFR Datasheet - Page 37

• Manufacturer Part Number: H5PS1G63EFR
• Description: 1Gb DDR2 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.4 / Nov 2008
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when
the device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to
calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Fig-
ure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driv-
ing (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent.
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input
signal crossing at the V
the input signal crossing at the V
applied to the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input
signal crossing at the V
to the differential data strobe crosspoint for a falling signal applied to the device under test.
tRPST end point
tHZ , tRPST end point = 2*T1-T2
tHZ
T1
DQS
DQS
IH
IH
(ac) level to the differential data strobe crosspoint for a rising signal, and from
(dc) level to the differential data strobe crosspoint for a rising signal and V
T2
VOH + xmV
VOL + 1xmV
VOL + 2xmV
VOH + 2xmV
Differential Input waveform timing
IL
(ac) level to the differential data strobe crosspoint for a falling signal
tDS
tDH
tDS
VTT + 2xmV
VTT - 2xmV
tLZ , tRPRE begin point = 2*T1-T2
VTT + xmV
VTT -xmV
tDH
T1
T2
V
V
V
V
V
V
V
IL(ac)
IH(ac)
IH(dc)
DDQ
REF
IL(dc)
SS
(dc)
tLZ
tRPRE begin point
max
max
min
min
H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
IL
(dc)
37