H5PS1G63EFR HYNIX [Hynix Semiconductor], H5PS1G63EFR Datasheet - Page 8

• Manufacturer Part Number: H5PS1G63EFR
• Description: 1Gb DDR2 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 0.4 / Nov 2008
1.3 PIN DESCRIPTION
(UDQS),(UDQS)
(RDQS),(RDQS)
(LDQS),(LDQS)
RAS, CAS, WE
(LDM, UDM)
DQS, (DQS)
BA0 - BA2
A0 -A15
CK, CK
ODT
PIN
CKE
DM
DQ
CS
Input/Output
Input/Output
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is
synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchro-
nous for SELF REFRESH exit. After V
sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh
entry and exit, V
READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER
DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
On Die Termination Control: ODT (registered HIGH) enables on die termination resistance
internal to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS,
RDQS, and DM signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ,
UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended
Mode Register(EMR(1)) is programmed to disable ODT.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input Data is masked when DM is
sampled High coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing. For x8 device, the function of DM or RDQS/ RDQS is enabled by EMR command to EMR(1).
Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE
command is being applied (For 256Mb and 512Mb, BA2 is not applied). Bank address also deter-
mines if one of the mode register or extended mode register is to be accessed during a MR or
EMR command cycle.
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory
array in the respective bank. A10 is sampled during a precharge command to determine whether
the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to
be precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code
during MRS or EMRS commands.
Data input / output: Bi-directional data bus
Data Strobe: Output with read data, input with write data. Edge aligned with read data, cen-
tered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds
to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled via the
EMR(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in
single ended mode or paired with optional complementary signals DQS, LDQS,UDQS and RDQS
to provide differential pair signaling to the system during both reads and writes. An EMR(1) con-
trol bit enables or disables all complementary data strobe signals.
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMR(1)
EMR(1)
REF
must be maintained to this input. CKE must be maintained HIGH throughout
"single-ended DQS signals" refers to any of the following with A10 = 1 of
x4 DQS/DQS
x8 DQS/DQS
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
x4 DQS
x8 DQS
x8 DQS, RDQS,
x16 LDQS and UDQS
REF
has become stable during the power on and initialization
DESCRIPTION
if EMR(1)[A11] = 0
if EMR(1)[A11] = 1
if EMR(1)[A11] = 0
if EMR(1)[A11] = 1
H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
8