ICX224 SONY [Sony Corporation], ICX224 Datasheet - Page 45
ICX224
Manufacturer Part Number
ICX224
Description
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Manufacturer
SONY [Sony Corporation]
Datasheet
1.ICX224.pdf
(49 pages)
- Current page: 45 of 49
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Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3410GA by the CCD signal processor block serial interface, the CXD3410GA
loads D04 and subsequent data to each data register as shown in the table below according to the combination
of D01 to D03 .
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3410GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are –6dB, 0dB, +20dB, +34dB and +42dB.
MSB
D06 D07
D15
D01
0
0
1
0
0
0
0
1
1
Normal operating mode
Standby mode
1
D02
X
0
0
1
1
D08 D09 D10 D11 D12 D13 D14 D15
1
D03
X
0
1
0
1
1
Loading to standby control data register
Loading to PGA gain setting data register
Loading to OB clamp level setting data register
Loading to input pulse polarity setting data register
Access prohibited
C
0
Description of operation
0
Description of operation
0
0
3
– 45 –
1
LSB
1
GAIN is expressed as 1C3h .
CXD3410GA
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