M5M44260CJ-5 MITSUBISHI [Mitsubishi Electric Semiconductor], M5M44260CJ-5 Datasheet

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M5M44260CJ-5

Manufacturer Part Number
M5M44260CJ-5
Description
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
1.M5M44260CJ-5.pdf (29 pages)

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MIT
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2 000
1
M5M44260CJ,TP-5,-5S : Under development
DESCRIPTION
Microcomputer memory, Refresh memory for CRT
FEATURES
PIN DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
512 cycles every 8.2ms.
XX=J,TP
APPLICATION
The use of double-layer metalization process technology and a
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
Operating power dissipation
Self refresh capability *
Extended refresh capability
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A
512 refresh cycles every 128ms (A
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
This device has 2CAS and 1W terminals with a refresh cycle of
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
DQ
RAS
LCAS
UCAS
W
OE
V
A
V
Pin name
CC
0
SS
: option) only
Type name
CMOS Input level
CMOS Input level
M5M44260Cxx-5,-5S
M5M44260Cxx-6,-6S
M5M44260Cxx-7,-7S
Self refresh current
Extended refresh current
~A
1
~DQ
8
16
Lower byte control
Address inputs
Data inputs / outputs
Row address strobe input
column address strobe input
Upper byte control
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
column address strobe input
(max.ns)
access
RAS
time
70
50
60
Function
(max.ns)
access
CAS
time
13
15
20
0
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Address
(max.ns)
0
~A
access
~A
time
25
30
35
8
8
)
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
) *
(max.ns)
access
time
13
15
20
OE
(min.ns)
550µW (Max) *
Cycle
110
130
688mW (Max)
605mW (Max)
523mW (Max)
time
5.5mW (Max)
150µA (Max)
150µA (Max)
90
M5M44260CJ,TP-5,-6,-7,
(typ.mW)
dissipa-
Power
625
550
475
tion
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
Outline 44P3W-R (400mil TSOP Nomal Bend)
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
RAS
DQ4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Outline 40P0K (400mil SOJ)
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
A
A
A
A
A
A
A
A
W
W
1
2
3
4
5
6
7
8
0
1
2
3
1
2
3
5
6
7
8
0
1
2
3
10
11
12
13
14
15
16
17
18
19
20
10
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
-5S,-6S,-7S
MITSUBISHI LSIs
25
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
23
MITSUBISHI LSIs
NC: NO CONNECTION
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
V
V
A
A
A
A
A
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
SS
SS
8
7
6
5
4
SS
SS
8
7
6
5
4
SS
SS
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
(0V)
(0V)
(0V)
(0V)
(0V)
(0V)

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M5M44260CJ-5 Summary of contents

Page 1

... Early-write mode, LCAS / UCAS and OE to control output buffer impedance 512 refresh cycles every 8.2ms (A 512 refresh cycles every 128ms (A Byte or word control for Read/Write operation (2CAS, 1W type Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S : option) only APPLICATION Microcomputer memory, Refresh memory for CRT PIN DESCRIPTION ...

Page 2

... FUNCTION In addition to normal read,write and read-modify-write operations the M5M44260CJ, TP provides a number of other functions, e.g., Table 1 Input conditions for each mode Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write RAS only refresh Hidden refresh ...

Page 3

... I are dependent on output loading. Specified values are obtained with the output open. CC1 (AV) CC4 (AV) 5: Column Address can be changed once or less while RAS=V 3 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Conditions With respect to V Ta=25˚C (Ta=0~70˚ ...

Page 4

... CP(max 12: and defines the time at which the output achieves the high impedance state (I OFF(max) OEZ (max OL(max) 4 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM =5V±10%, V =0V, unless otherwise noted) SS Test conditions f=1MHz ...

Page 5

... OCH t RAS hold time after OE low ORH t t Note 21: Either or must be satisfied for a read cycle. RCH RRH 5 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Parameter M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S (Note 15) (Note 16) (Note 17) (Note 18) (Note 18) (Note 19) (Note 19) ...

Page 6

... DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM ...

Page 7

... CBR self refresh RAS low pulse width RASS t CBR self refresh RAS high precharge time RPS t CBR self refresh CAS hold time CHS 7 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Parameter Min 35 71 (Note 25) ...

Page 8

... ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t RAD t CAH t RAH t ASC ROW COLUMN ADDRESS ADDRESS t RCS t DZC ...

Page 9

... DQ ~ (INPUTS ~ ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t RAD RAH ASC CAH ROW COLUMN ADDRESS t RCS t DZC t CAC t AA ...

Page 10

... ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM RAS t CSH t RCD t CAS t CAH t ASC COLUMN ADDRESS t t WCS WCH DATA VALID ...

Page 11

... DQ ~ (INPUTS ~ ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t t RAH CAH t ASC COLUMN ROW ADDRESS t WCS t Hi DATA VALID Hi-Z ...

Page 12

... ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t t RAH CAH t ASC ROW COLUMN ADDRESS t RCS t DZC Hi-Z t CLZ Hi-Z t DZO MITSUBISHI LSIs ...

Page 13

... V IH ( (INPUTS ~ ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t t CAH RAH t ASC ROW COLUMN ADDRESS t RCS Hi-Z t DZC Hi-Z t CLZ Hi OEZ ...

Page 14

... ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t RAD t t RAH CAH t ASC ROW COLUMN ADDRESS ADDRESS t AWD t CWD t RCS ...

Page 15

... DQ ~ (INPUTS ~ ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t RAD t t CAH RAH t ASC ROW COLUMN ADDRESS ADDRESS t AWD t CWD t RCS t ...

Page 16

... ADDRESS ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t RAH Hi-Z MITSUBISHI LSIs RPC t CRP t ASR ROW ADDRESS ...

Page 17

... OFF ~ (OUTPUTS OEZ t ODD M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM RAS t t CSR RPC t CHR MITSUBISHI LSIs RAS RP t CRP t t CHR RPC ...

Page 18

... Note 30: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. 18 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM (Note 30 RAS t t RCD RSH t RAD ...

Page 19

... ~ (INPUTS Hi (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH RCD CAS CP t RAD t t ASC CAH t ASC COLUMN ADDRESS1 t RCS t RCH t ...

Page 20

... V (INPUTS ~ Hi-Z OH ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH RCD CAS CP t RAD ASC CAH ASC COLUMN ADDRESS1 ADDRESS2 t t RCS ...

Page 21

... ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t CSH t t RCD CAS t t CAH t ASC RAH ROW COLUMN ADDRESS1 t t WCS WCH ...

Page 22

... ~ ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t CSH t t RCD CAS CAH RAH ASC ROW COLUMN ADDRESS1 t t WCH WCS ...

Page 23

... ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t CSH t t RCD CAS t t RAH CAH t ASC ROW COLUMN ADDRESS1 t RCS t WCH t DZC t DS ...

Page 24

... IH ( (INPUTS ~ Hi-Z ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t t RCD CAS t ASC t CAH COLUMN ADDRESS1 t CWL t RCS t WCH Hi-Z t DZC t DS Hi-Z DATA ...

Page 25

... ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t CSH t t CAS RCD t RAD t t RAH CAH t ASC ROW COLUMN ADDRESS1 t AWD t t CWD RCS ...

Page 26

... V (INPUTS ~ ( (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t CSH t t CAS RCD t RAD t t RAH CAH t ASC ROW COLUMN ADDRESS1 t AWD t t CWD RCS ...

Page 27

... OFF ~ (OUTPUTS OEZ t ODD M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RASS t CSR MITSUBISHI LSIs t RPS t RPC t t CHS CRP t ASR ROW ADDRESS Hi-Z COLUMN ADDRESS t RCS ...

Page 28

... CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within t (shown in table 2). NSD 28 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Self Refresh Cycle t t 100µs ...

Page 29

... RAS signal at SNB the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 8.2 ms. 29 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Self Refresh t 100µs ...

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