HY5DU281622DLT HYNIX [Hynix Semiconductor], HY5DU281622DLT Datasheet
HY5DU281622DLT
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HY5DU281622DLT Summary of contents
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DDR SDRAM HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.0/Apr. 2003 ...
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Revision History 1. Rev 0.0 (Apr. 2003) 1) Datasheet Release in Preliminary version Rev. 0.0 / Apr. 2003 HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T 2 ...
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DESCRIPTION The HY5DU28422D(L)T, HY5DU28822D(L)T and HY5DU281622D(L)T are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced ...
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PIN CONFIGURATION x4 x8 VDD VDD NC DQ0 VDDQ VDDQ NC NC DQ0 DQ1 VSSQ VSSQ DQ2 VDDQ VDDQ NC NC DQ1 DQ3 VSSQ VSSQ VDDQ VDDQ VDD VDD ...
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PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0 ~ A11 Input /RAS, /CAS, /WE Input DM Input (LDM,UDM) DQS I/O (LDQS,UDQS Supply Supply DDQ SSQ ...
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FUNCTIONAL BLOCK DIAGRAM (32Mx4) 4Banks x 8Mbit x 4 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE /CS Command /RAS Decoder /CAS /WE DM A0~A11 Address Buffer BA0,BA1 Rev. 0.0 / Apr. 2003 Write Data Register 2-bit Prefetch Unit ...
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FUNCTIONAL BLOCK DIAGRAM (16Mx8) 4Banks x 4Mbit x 8 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE /CS Command /RAS Decoder /CAS /WE DM A0~A11 Address Buffer BA0, BA1 Rev. 0.0 / Apr. 2003 Write Data Register 2-bit Prefetch ...
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FUNCTIONAL BLOCK DIAGRAM (8Mx16) 4Banks x 2Mbit x 16 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE /CS Command /RAS Decoder /CAS /WE LDM UDM A0~A11 Address Buffer BA0, BA1 Rev. 0.0 / Apr. 2003 Write Data Register 2-bit ...
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SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self ...
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WRITE MASK TRUTH TABLE Function CKEn-1 Data Write Data-In Mask Note : 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM ...
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OPERATION COMMAND TRUTH TABLE-I Current /CS /RAS State IDLE ROW L H ACTIVE L ...
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OPERATION COMMAND TRUTH TABLE-II Current /CS /RAS State WRITE READ WITH L H AUTOPRE CHARGE ...
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OPERATION COMMAND TRUTH TABLE-III Current /CS /RAS State ROW L H ACTIVATING WRITE L H RECOVERING ...
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OPERATION COMMAND TRUTH TABLE-IV Current /CS /RAS State WRITE MODE L H REGISTER ACCESSING ...
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CKE FUNCTION TRUTH TABLE Current CKEn- CKEn State SELF REFRESH POWER DOWN ...
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SIMPLIFIED STATE DIAGRAM MODE REGISTER SET POWER DOWN READ WRITE READAP WRITE WRITEAP PRE(PALL) Rev. 0.0 / Apr. 2003 MRS SREF IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally ...
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Issue 2 or more Auto Refresh commands. 8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK CKE CMD DM ADDR A10 BA0,BA1 ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column ...
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CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2, 2 ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Voltage on V relative to V DDQ SS Output Short Circuit Current Power Dissipation Soldering Temperature ...
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DC CHARACTERISTICS II 32Mx4 Parameter Symbol Operating Current IDD0 Operating Current I DD1 Precharge Power Down I DD2P Standby Current Idle Standby Current I DD2N Idle Standby Current I DD2F Idle Quiet Standby Current I DD2Q Active Power Down I ...
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DC CHARACTERISTICS II 16Mx8 Parameter Symbol One bank; Active - Precharge ; tRC=tRC(min); tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per Operating Current IDD0 clock cycle; address and control inputs changing once per clock cycle One bank; Active - ...
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DC CHARACTERISTICS II 8Mx16 Parameter Symbol One bank; Active - Precharge ; tRC=tRC(min); tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per Operating Current IDD0 clock cycle; address and control inputs changing once per clock cycle One bank; Active - ...
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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7 IDD1 : Operating current: One bank operation 1. Typical Case : VDD = 2.6V, T=25 2. Worst Case : VDD = 2.7V Only one bank is accessed with ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note ...
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AC CHARACTERISTICS I Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay ...
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Parameter Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In DQS falling edge to CK setup time DQS falling edge hold time from CK Data-In Setup Time to DQS-In ...
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CK, /CK slew rates are >=1.0V/ns 6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. Data latched at both rising and falling ...
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CAPACITANCE o (T =25 C, f=100MHz ) A Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitanc Delta Input / Output Capacitance Note : 1. VDD = min. to max., VDDQ = ...
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PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Rev. 0.0 / Apr. 2003 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T Unit : mm(Inch) 11.94 (0.470) ...