HY5DU561622CT-D HYNIX [Hynix Semiconductor], HY5DU561622CT-D Datasheet
HY5DU561622CT-D
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HY5DU561622CT-D Summary of contents
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... HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 ...
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... JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch • Full and Half strength driver option controlled by EMRS OPERATING FREQUENCY Package Grade - D4 400mil 66pin - D43 TSOP-II HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 PRELIMINARY Remark Speed (CL-tRCD-tRP) 200MHz DDR400 (3-4-4) 200MHz DDR400 (3-3-3) 3 ...
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... VDD 33 ROW AND COLUMN ADDRESS TABLE 64Mx4 16M 4banks 4banks A0 - A12 A0-A9, A11 BA0, BA1 A10 8K HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 x16 x8 x4 VSS VSS 66 VSS DQ15 DQ7 65 NC VSSQ VSSQ 64 VSSQ DQ14 DQ13 ...
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... DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 4 ...
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... Bank0 Control 16Mx4 / Bank1 16Mx4 / Bank2 16Mx4 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 4 DQS DQ[0:3] DQS Data Strobe Transmitter Data Strobe DQS Receiver 5 ...
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... Bank0 Control 8Mx8 / Bank1 8Mx8 / Bank2 8Mx8 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 8 DQS DQ[0:7] DQS Data Strobe Transmitter Data Strobe DQS Receiver 6 ...
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... Bank2 4Mx16 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 16 LDQS, UDQS LDM, UDM 32 16 DQ[0:15] LDQS, UDQS Data Strobe Transmitter LDQS Data Strobe UDQS Receiver 7 ...
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... HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 A10/ CAS WE ADDR code code ...
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... Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 0.3 / Oct. 2003 CKEn /CS, /RAS, /CAS, / HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 ADD A10 Note 1 1 ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS ...
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... READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ...
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... OPCODE BA, CA, AP READ/READAP HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL ...
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... L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ...
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... HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 15 ...
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... DLL) 6. Issue Precharge commands for all banks of the device. Rev. 0.3 / Oct. 2003 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 16 ...
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... EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC ...
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... Reserved Operating Mode Normal Operation Normal Operation/ Reset DLL Vendor specific Test Mode All other states reserved HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 CAS Latency BT Burst Length A3 Burst Type 0 Sequential 1 Interleave Burst Length Sequential ...
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... HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Interleave ...
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... Selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver and the half strength driver are included in this document. Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 20 ...
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... This part do not support /QFC function, A2 must be programmed to Zero. Rev. 0.3 / Oct. 2003 Operating Mode Operating Mode Normal Operation Valid All other states reserved - HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DLL A0 DLL enable 0 Enable 1 Diable Output Driver A1 ...
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... VID(DC) 0.36 VI(RATIO the transmitting device, and to track variations in the dc level of the same. DDQ HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Rating Unit -55 ~ 125 o C -0.5 ~ 3.6 V -0.5 ~ 3.6 V -0 260 ⋅ ⋅ sec = 0V) SS ...
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... Four bank interleaving with BL=4, Refer to I DD7 Four Bank Operation the following page for detailed test condition Rev. 0.3 / Oct. 2003 o (TA Voltage referenced to V Test Condition Normal Low Power HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) SS Speed Unit Note -D4 -D43 115 120 mA 125 130 mA 10 ...
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... Four bank interleaving with BL=4, Refer to I DD7 Four Bank Operation the following page for detailed test condition Rev. 0.3 / Oct. 2003 o (TA Voltage referenced to V Test Condition Normal Low Power HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) SS Speed Unit Note -D4 -D43 115 120 mA 125 130 mA 10 ...
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... Four bank interleaving with BL=4, Refer to I DD7 Four Bank Operation the following page for detailed test condition Rev. 0.3 / Oct. 2003 o (TA Voltage referenced to V Test Condition Normal Low Power HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) SS Speed Unit Note -D4 -D43 120 125 mA 135 140 mA 10 ...
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... DDR400(200Mhz, CL=3) : tCK = 5ns, CL=3, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : RA0 A2 RA1 A3 RA2 N RA3 repeat the same timing with random address changing 50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 26 ...
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... Rev. 0.3 / Oct. 2003 o (TA Voltage referenced to V Symbol Min 0.31 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ o (TA Voltage referenced to VSS = 0V HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 = 0V) SS Max Unit 0.31 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit x 0.5 V DDQ x 0.5 V DDQ + 0.31 V REF - 0.31 ...
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... Max. area=2.4V- Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition Rev. 0.3 / Oct. 2003 Parameter Max. amplitude=1. Time(ns) Parameter Max. amplitude=1. Time(ns) HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Specification DDR333 DDR200/266 1.5V 1.5V 1.5V 1. Overshoot V DD Ground Undershoot 5 6 Specification DDR333 1 ...
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... HP tQH -t QHS min tHP (tCL,tCH) tQHS - tHZ tLZ tAC(min) tAC(Max) tAC(min) tIS 0.6 tIH 0 0.7 IH HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DDR400 (D43) Unit Max Min Max - 70K 40 70K ns tRCD tRAS(min ...
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... Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit self refresh to non-READ command Exit self refresh to READ command Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval Rev. 0.3 / Oct. 2003 HY5DU561622CT-D4/D43 DDR400 (D4) DDR400 (D43) Symbol Min Max Min t 2 ...
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... Rev. 0.3 / Oct. 2003 Delta tIS Delta tIH +50 0 +100 0 Delta tDS Delta tDH +75 +75 +150 +150 Delta tDS Delta tDH ps ps +50 +50 Delta tDS Delta tDH +50 +50 +100 +100 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 31 ...
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... These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 32 ...
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... CK, /CK, CKE CK, /CK All other input-only pins All other input-only pins DQ, DQS, DM DQ, DQS VDDQ/2, V peak-to-peak = 0. =50 Ω Zo=50 Ω V REF C =30pF L HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Symbol Min Max C 2.0 3.0 I1 Delta 2.0 3.0 I1 Delta 4.0 5.0 IO ...
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... Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 0.3 / Oct. 2003 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) 0.120 (0.0047) 34 ...