HY5DU561622FLTP-4 HYNIX [Hynix Semiconductor], HY5DU561622FLTP-4 Datasheet
HY5DU561622FLTP-4
Related parts for HY5DU561622FLTP-4
HY5DU561622FLTP-4 Summary of contents
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HY5DU561622FTP-5 / HY5DU561622FTP-4 256M(16Mx16) DDR SDRAM HY5DU561622F(L)TP-5 HY5DU561622F(L)TP-4 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. ...
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Revision History Revision No. 1.0 First Version Release Correction 1.1 - P.3 Ordering Information Rev. 1.1 / Mar. 2008 History 1HY5DU561622FTP-5 HY5DU561622FTP-4 Draft Date Remark Nov. 2007 Mar. 2008 2 ...
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DESCRIPTION The Hynix HY5DU561622FTP-5, -4 series are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 16Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling ...
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PIN CONFIGURATION V DD DQ0 VDDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 NC V DDQ LDQS LDM /WE / CAS / RAS / CS NC BA0 BA1 A10/AP A0 ...
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PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0 ~ A12 Input /RAS, /CAS, /WE Input LDM, UDM Input LDQS, UDQS I/O DQ0 ~ DQ15 I Supply Supply ...
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FUNCTIONAL BLOCK DIAGRAM 4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE /CS Command Decoder /RAS /CAS LDM UDM Register A0-12 Address Buffer BA0,BA1 Rev. 1.1 / Mar. 2008 W rite Data Register 2-bit Prefetch ...
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SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self ...
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WRITE MASK TRUTH TABLE Function CKEn-1 Data Write H Data-In Mask H Lower Byte Write / H Upper Byte-In Mask Upper Byte Write / H Lower Byte-In Mask Note : 1. Write Mask command masks burst write data with reference ...
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OPERATION COMMAND TRUTH TABLE - I Current /CS /RAS State IDLE ROW L H ...
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OPERATION COMMAND TRUTH TABLE - II Current /CS /RAS State WRITE READ WITH L H AUTOPRE CHARGE ...
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OPERATION COMMAND TRUTH TABLE - III Current /CS /RAS State ROW L H ACTIVATING WRITE L ...
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OPERATION COMMAND TRUTH TABLE - IV Current /CS /RAS State WRITE MODE L H REGISTER ACCESSING ...
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CKE FUNCTION TRUTH TABLE Current CKEn-1 CKEn State SELF REFRESH POWER DOWN ...
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SIMPLIFIED STATE DIAGRAM ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF ...
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Issue 2 or more Auto Refresh commands. 8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low. Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS tIH LVCMOS Low Level CKE ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column ...
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The latency can be programmed clocks Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Voltage on V relative to V DDQ SS Output Short Circuit Current Power Dissipation Soldering Temperature ...
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DC CHARACTERISTICS II Parameter Symbol Operating Current I DD1 Precharge Power Down I DD2P Standby Current Idle Standby Current I DD2N Active Power Down I DD3P Standby Current Active Standby Current I DD3N I DD4R Operating Current IDD4W Auto Refresh ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note ...
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AC CHARACTERISTICS - I Parameter Row Cycle Time (Manual Precharge) Row Cycle Time (Auto Precharge) Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address ...
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Parameter Data-In Hold Time to DQS-In (DQ & DM) Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any ...
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AC CHARACTERISTICS - II tRC Frequency CL (Manual Precharge) 250MHz 4 15 (4.0ns) 200MHz 3 12 (5.0ns) Rev. 1.1 / Mar. 2008 tRC_APCG tRFC tRAS (AUTO Precharge 40ns 14 14 40ns 1HY5DU561622FTP-5 HY5DU561622FTP-4 tRCDRD tRCDWT tRP tDAL 5 ...
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CAPACITANCE o (T =25 C, f=1MHz ) A Parameter Input Clock Capacitance Input Capacitance Input / Output Capacitanc Note : min. to max 2.3V to 2.7V DDQ 2. Pins not under test are ...
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PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 1.1 / Mar. 2008 BASE PLANE 22.33 (0.879) 22.12 (0.871) ...