AX88140AP ETC, AX88140AP Datasheet
AX88140AP
Related parts for AX88140AP
AX88140AP Summary of contents
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PCI Bus Fast Ethernet MAC Controller This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products specification without notice. No liability is assumed as a result of the use of this product. No ...
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... AX88140A 1.0 INTRODUCTION ................................................................................................................................................ 6 1 ...................................................................................................................................... 6 ENERAL ESCRIPTION 1.2 F ............................................................................................................................................................ 7 EATURES 1 ............................................................................................................................................... 8 LOCK IAGRAM 1.4 AX88140AQ ONNECTION 1.5 AX88140AP ONNECTION 2.0 SIGNAL DESCRIPTION .................................................................................................................................. 11 2 160- IGNAL ESCRIPTIONS FOR 2.2 PCI ...................................................................................................................................... 12 INTERFACE GROUP 2.3 B ROM , S ROM , G OOT ERIAL 2.4 MII/SYM/SRL INTERFACE SIGNALS GROUP 2 NC, P XTENDED OWER PINS GROUP 3.0 CONFIGURATION OPERATION .................................................................................................................. 17 3 ...
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AX88140A 6.0 ELECTRICAL SPECIFICATION AND TIMINGS ...................................................................................... 35 6 BSOLUTE AXIMUM ATINGS 6 ENERAL PERATION ONDITIONS 6 ...................................................................................................................................... 35 HARACTERISTICS 6.4 A. IMING HARACTERISTICS 6.4.1 PCI CLOCK .............................................................................................................................................. 36 6.4.2 ...
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... AX88140A AX88140A LOCK IAGRAM AX88140AQ CONNECTION DIAGRAM FOR AX88140AP CONNECTION DIAGRAM FOR ESCRIPTOR TRUCTURE XAMPLE ECEIVE ESCRIPTOR ORMAT RANSMIT ESCRIPTOR ORMAT PCS / S IG PPLICATION FOR ...
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AX88140A PCI ................................................................................................................................... 13 AB INTERFACE GROUP ROM , S ROM , G AB OOT ERIAL MII/SYM/SRL AB INTERFACE SIGNALS GROUP NC XTENDED ...
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AX88140A 1.0 Introduction 1.1 General Description: l The AX88140A Fast Ethernet Controller is a high performance and highly integrated PCI Bus Ethernet Controller chip. l The AX88140A is cost effective, high performance solution for PCI add-in adapters, PC motherboards, or ...
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AX88140A 1.2 Features l Single chip PCI bus Fast Ethernet Controller. l Direct interface to PCI bus. l Support both 10Mbps and 100Mbps data rate. l Full or Half duplex operation supported for both10Mbps and 100Mbps operation. l Provides a ...
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AX88140A 1.3 Block Diagram: SERIAL ROOM ROM I/F PCI PCI BUS BUS Interface BOOT ROM Interface Serial BOOT ROM I/F Receive FIFO MAC Buffer Management Controller DMA Engine Transmit FIFO General Purpose REG General purpose I/O pins Fig - 1 ...
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AX88140A 1.4 AX88140AQ Pin Connection Diagram for 160-pin The AX88140A is housed in the 160-pin plastic quad flat pack. pin connection diagram int# 4 rst# 5 vdd 6 vss 7 pci_clk 8 vdd ...
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... Fig - 3 AX88140AP Pin connection diagram for 144-pin ASIX 88140AP 10 ASIX ELECTRONICS CORPORATION PRELIMINARY shows the AX88140A Fig - 3 vss 108 vdd 107 mdc 106 mdio 105 nc 104 br_a<1> ...
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AX88140A 2.0 Signal Description 2.1 Signal Descriptions for 160-pin and 144-pin The following terms describe the AX88140A pin-out: l Address phase Address and appropriate bus commands are driven during this cycle. l Data phase Data and the appropriate byte enable ...
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AX88140A 2.2 PCI interface group SIGNAL TYPE PIN NUMBER FOR 160 PIN AD<31> I/O 12, AD<30> 13, AD<29> 15, AD<28> 16, AD<27> 18, AD<26> 19, AD<25> 21, AD<24> 22, AD<23> 26, AD<22> 27, AD<21> 28, AD<20> 29, AD<19> 31, AD<18> ...
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AX88140A PAR I/O 53 PCI_CLK I 7 PERR# I/O 51 REQ RST SERR# I/O 52 STOP# I/O 49 TRDY# I/O 47 IRDY# to indicate that it is ready to accept data. 47 Parity is an even ...
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AX88140A 2.3 Boot ROM , Serial ROM , General-purpose signals group SIGNAL TYPE PIN NUMBER FOR 160 PIN BR_A<0> 0 112 BR_A<1> 0 113 BR_AD<7> I/O 110, BR_AD<6> 109, BR_AD<5> 106, BR_AD<4> 105, BR_AD<3> 104, BR_AD<2> 103, BR_AD<1> 102, BR_AD<0> ...
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AX88140A MRCLK/SYMRCLK I MRXD<3>/SYMRXD<3> I MRXD<2>/SYMRXD<2> MRXD<1>/SYMRXD<1> MRXD<0>/SYMRXD<0> MTCLK/SYMTCLK I MTXD<3>/SYMTXD<3> O MTXD<2>/SYMTXD<2> MTXD<1>/SYMTXD<1> MTXD<0>/SYMTXD<0> MTXEN/SYMTXEN O RCV_MATCH SRL_CLSN I SRL_RCLK I SRL_RXD I SRL_RXEN I SRL_TCLK I SRL_TXD O SRL_TXEN O SYMRXD <4> I SYMTXD<4> O ...
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AX88140A 2.5 Extended , NC, Power pins group SIGNAL TYPE PIN NUMBER FOR 160 PIN EC<15:0> O 160,159,122, 121,120,119, 82,81,80,79,42,41 ,40,39,2 114,138,155,156, 157,158 VDD P 5,8,20,30,33, 50,62,73,85, 95,108,117, 135,143 VDD VSS P 6,11,14,17,25, 34,35,38,43, 55,59,65,70, 76,84,94,100, ...
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AX88140A 3.0 Configuration Operation 1. Software reset (REG0<0>) has no effect on the configuration registers. 2. Hardware reset puts the configuration registers in default values. 3. The configuration registers could be accessed in byte, word , and long-word. 3.1 Configuration ...
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AX88140A 3.2 Configuration Space 3.2.1 Configuration ID Register (CSID) FIELD R/W 31:16 R Device ID : Provides the unique AX88140A ID number (1400H) 15:0 R Vender ID : Provides the manufacturer of the AX88140A (125BH) Tab - 6 CSID Configuration ...
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AX88140A 3.2.5 Configuration Base I/O Address Register (CBIO) FIELD R/W 31:7 R/W Configuration Base I/O Address : Defines the address assignment mapping of AX88140A‘s regs. 6:1 R This field value is 0 when read 0 R I/O Space Indicator : ...
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AX88140A 4.0 Registers Operation 1. The REGs are quad-word aligned, 32-bits long, and must be accessed using long-word instruction with quad-word aligned addresses only. 2. Reserved bits should be written with 0.; Reserved bits are UNPREDICTABLE on read access. 3. ...
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AX88140A 4.2 Host REGs 4.2.1 Bus Mode Register (REG0) FIELD R/W/C 31:22 - RESERVED 21 R/W RML - Read Multiple When set, the AX88140A supports the memory-read-multiple command on the PCI bus. This bus command is used in memory read ...
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AX88140A 4.2.3 Receive Poll Demand (REG2) FIELD R/W/C 31:0 W RPD - Receive Poll Demand When written with any value, the AX88140A checks for receive descriptors to be required descriptor is available, the receive process returns to the ...
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AX88140A 4.2.6 Status Register (REG5) 1. The status register contains all the status bits that the AX88140A reports to the host. 2. Most of the fields in this register cause the host to be interrupted. 3. REG5 bits are not ...
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AX88140A 3 R/W/C TJT - Transmit Jabber Time-out Indicates that the transmit jabber timer expired, meaning that the AX88140A transmitter had been excessively active. The transmission process is aborted and placed in the stopped state. This event causes the transmit ...
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AX88140A 8 R Receive broadcast packet 7 R Pass All Multicast 6 R Promiscuous Mode 5:4 - Reserved.--Written as “0” for future compatibility concern Pass Bad Frames 2 - Reserved.--Written ...
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AX88140A 4.2.8 Interrupt Enable Register (REG7) 1. The interrupt enable register (REG7) enables the interrupts reported by REG5. 2. Setting bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled. Field R/W/C 31:17 ...
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AX88140A 4.2.10 Serial ROM and MII Management Register (REG9) 1. The register provides an interface to the Microwire serial ROM and to the physical layer protocol (PHY). It selects the device and contains both the commands and data to be ...
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AX88140A Tab - 26 REG11 General -Purpose Timer Register Description 4.2.12 General -Purpose Port Register (REG12) Field R/W/C 31:9 - Reserved.--Written as “0” for future compatibility concern. 8 R/W GPC - General Purpose Control . When a hardware reset is ...
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AX88140A 1 RESERVED MULTICAST 2 ADDRESS FILTERING TABLE FILTERING TABLE BIT multicast address 3 filtering table bit 56 - filtering table bit Tab - 31 Layout of Filtering Buffer RESERVED PHYSICAL ADDRESS BYTE ...
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AX88140A 5.0 Host Communication Descriptor lists and data buffers, collectively called the host communication, reside in the host memory and manage the actions and status related to buffer management. 5.1 Descriptor Lists and Data Buffers The AX88140A transfers data frames ...
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AX88140A 5.2 Receive Descriptors The receive descriptor provides one buffer, one byte-count buffer, and one address pointer in each descriptor. Descriptors and receive buffers addresses must be long-word aligned. Receive Descriptor Format 31 O RDES0 W N RDES1 Control bits ...
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AX88140A Multicast Frame Indicates that this frame is a multicast address. This field is valid only when last descriptor (RDES0<8>) is set First Descriptor Last Descriptor Frame Too ...
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AX88140A 5.3 Transmit Descriptors Providing one buffer, one byte-count buffer, and two address pointers in each descriptor . Transmit Descriptor Format 31 O TDES0 W N TDES1 Control bits TDES2 TDES3 5.3.1 Transmit Descriptor 0 (TDES0) TDES0 contains transmitted frame ...
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AX88140A Under-flow Error When set, indicates that the transmitter aborted the message because data arrived late from memory. Under- flow error indicates that the AX88140A encountered an empty transmit FIFO while transmitting a frame. The transmission process ...
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AX88140A 6.0 Electrical Specification and Timings 6.1 Absolute Maximum Ratings Description Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) Note : Stress above those listed under Absolute Maximum Ratings may cause permanent ...
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AX88140A 6.4 A.C. Timing Characteristics 6.4.1 PCI CLOCK Symbol Description Tcyc CYCLE TIME Thigh PCI_CLK HIGH TIME Tlow PCI_CLK LOW TIME Tr/Tf PCI_CLK SLEW RATE 6.4.2 PCI Timings PCI_CLK Tval (max) OUTPUT Ton INPUT Symbol Description Tval CLK TO SIGNAL ...
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AX88140A 6.4.4 MII/SYM Timing MTCLK/SYMTCLK MTXD<3:0>/SYMTXD<3:0> MTXEN/SYMTXEN MRCLK/SYMRCLK MRXD<3:0>/SYMRXD<3:0> MTXEN/SYMTXEN MRXERR,SD Symbol Description Ttclk Cycle time(100Mbps) Ttclk Cycle time(10Mbps) Ttch high time(100Mbps) Ttch high time(10Mbps) Trch low time(100Mbps) Trch low time(10Mbps) Ttv Clock to data valid Tth Data output hold ...
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AX88140A 6.4.5 10Mbps serial timing SRL_TCLK SRL_TXD SRL_TXEN SRL_RCLK SRL_RXD SRL_RXEN Symbol Description Tstc SRL_TCLK Cycle time Tstch Clock high time Tstcl Clock low time Tsto Data output delay Tsto1 SRL_TXEN data output delay Tsth Data output hold time Tsrc ...
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AX88140A 6.4.6 Boot ROM Read Cycles Boot ROM Byte Read Cycle br_ad<7:0> address 9-2 br_a1 br_a0 brce# Boot ROM Dword Read Cycle br_ad<7:0> address 9-2 br_a1 br_a0 brce# address 17-10 data address 1 address 0 address 17-10 data3 39 ASIX ...
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AX88140A 7.0 Package Information pin 1 b AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ...
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AX88140A APPENDIX A.1 Boot ROM read cycle ASIX 88140 Boot ROM Byte Read Cycle br_ad<7:0> address 9-2 br_a1 br_a0 brce# 74LS374 ...
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AX88140A A.2 Power Supply AX88140A power supply is +5V DC DEC 21140 power supply is +3.3V DC A.3 Boundary Scan Test Pins AX88140A do not support boundary scan test pins DEC 21140 supports boundary scan test pins PRELIMINARY 42 ASIX ...
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AX88140A APPENDIX B.1 Application for PCI Interface Features : l Direct interface to PCI Bus. l Support 33 MHz no wait state PCI Bus Interface. l Powerful on chip buffer management DMA. And PCI Bus master operation reduce CPU utilization. ...
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AX88140A B.2 Application for Boot ROM Interface AX88140A Boot ROM Byte Read Cycle BR_AD<7:0> address 9-2 BR_A1 BR_A0 BRCE# 74LS374 ...
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AX88140A B.4 Application for PHY Interface B.4.1 AX88140A, QSI6611, & MTD213 Application Fig - 7 Application for PCS / Serial Mode B.4.2 Application for MII Mode : LEVEL ONE LXT970 MII STA Fig - 8 Application for MII Mode with ...
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AX88140A B.4.3 Application for MII Mode : MYSON MTD972 + MTD971 MII STA Fig - 9 Application for MII Mode with MTD972 +MTD971 B.4.4 Application for MII Mode : DAVICOM DM9101 MII STA Fig - 10 Application for MII Mode ...