EP910 ALTERA [Altera Corporation], EP910 Datasheet
EP910
Available stocks
Related parts for EP910
EP910 Summary of contents
Page 1
... Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features Feature Usable gates Macrocells Maximum user I/O pins t (ns (MHz) CNT EPLD Family ® MAX+PLUS EP610 EP910 EP610I EP910I 300 450 100 76.9 Classic Data Sheet ® II EP1810 900 48 64 ...
Page 2
Classic EPLD Family Data Sheet General Description 746 TM The Altera Classic device family offers a solution to high-speed, low- power logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this ...
Page 3
Functional Description Altera Corporation For more information, see the Development System & Software Data The Classic architecture includes the following elements: Macrocells Programmable registers Output enable/clock select Feedback select Macrocells Classic macrocells, shown in both sequential and combinatorial logic ...
Page 4
Classic EPLD Family Data Sheet 748 The eight product terms of the programmable-AND array feed the 8-input OR gate, which then feeds one input to an XOR gate. The other input to the XOR gate is connected to a programmable ...
Page 5
... Figure 3. Classic Feedback Multiplexer Configurations Global Feedback Multiplexer Q Global I/O EP610 EP610I EP910 EP910I Altera Corporation Figure 2. Classic Output Enable/Clock Select AND Array OE = Product Term CLK = Global AND Array OE = Enabled CLK = Product Term Feedback Select Each macrocell in a Classic device provides feedback selection that is controlled by the feedback multiplexer ...
Page 6
... Classic EPLD Family Data Sheet Design Security Timing Model 750 EP610, EP610I, EP910, and EP910I devices have a global feedback configuration; either the macrocell output (Q) or the I/O pin input (I/O) can feed back to the AND array so that it is accessible to all other macrocells. ...
Page 7
Altera Corporation Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal ...
Page 8
Classic EPLD Family Data Sheet Figure 5. Classic Switching Waveforms t and t < Inputs are driven for a logic high and I/O Pin 0 V for a logic low. All timing characteristics ...
Page 9
Turbo Bit Option Generic Testing Device Programming Altera Corporation Many Classic devices contain a programmable Turbo Bit control the automatic power-down feature that enables the low-standby- power mode. When the Turbo Bit option is turned on, the low-standby- power mode ...
Page 10
Notes: ...
Page 11
Features Figure 7. EP610 Package Pin-Out Diagrams Package outlines not drawn to scale. Windows in ceramic packages only. VCC 1 24 CLK1 INPUT INPUT I/O I/O I I/O I I/O 6 ...
Page 12
Classic EPLD Family Data Sheet General Description Figure 8. EP610 Block Diagram Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages. 2 (3) INPUT 1 (2) CLK1 3 (4) 4 (5) 5 (6) ...
Page 13
Figure 10. Output Drive Characteristics of EP610 Devices Drive characteristics may exceed shown curves. EP610-15 & EP610-20 EPLDs 200 150 Typical I CC Output 100 Current (mA 0.45 V Output Voltage (V) O EP610I EPLDs 100 80 60 ...
Page 14
Classic EPLD Family Data Sheet Operating Conditions Table 2. EP610 & EP610I Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage ground current MAX output current, per ...
Page 15
Table 5. EP610 & EP610I Device Capacitance Symbol Parameter C Input pin capacitance IN C I/O pin capacitance I/O C CLK1 pin capacitance CLK1 C CLK2 pin capacitance CLK2 Table 6. EP610 Device I Supply Current CC Symbol Parameter I ...
Page 16
Classic EPLD Family Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC input is –0.3 V. During transitions, the inputs may undershoot ...
Page 17
Table 8. EP610-15 & EP610-20 External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered output PD2 t Input to output enable PZX t Input to output disable PXZ t Asynchronous output clear time ...
Page 18
Classic EPLD Family Data Sheet Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part Symbol Parameter t Register setup time SU t Register hold time H t Array clock delay IC t Global clock delay ICS t ...
Page 19
Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Logic array delay LAD t Output buffer and pad delay OD t Output ...
Page 20
Classic EPLD Family Data Sheet Table 12. EP610I External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered output PD2 t Input to output enable PZX t Input to output disable PXZ t Asynchronous ...
Page 21
Table 13. EP610 Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Logic array delay LAD t Output buffer and pad delay OD t Output buffer enable delay ...
Page 22
Notes: ...
Page 23
... Counter frequencies 76.9 MHz – Pipelined data rates 125 MHz Programmable I/O architecture with inputs or 24 outputs EP910 and EP910I devices are pin-, function-, and programming file- compatible Programmable clock option for independent clocking of all registers Macrocells individually programmable JK flipflops, or ...
Page 24
... INPUT 768 Altera EP910 devices can implement up to 450 usable gates of SSI and MSI logic functions. EP910 devices have 24 macrocells, 12 dedicated input pins, 24 I/O pins, and 2 global clock pins (see can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input ...
Page 25
... V O Altera Corporation Figure 13 shows the typical supply current (I EP910 devices. Figure 13. I vs. Frequency of EP910 Devices CC 100 10 Typical I CC Active (mA) 1.0 0.1 Figure 14 shows the typical output drive characteristics of EP910 devices. EP910I EPLDs I OL Typical I Output Current (mA ...
Page 26
... ground current MAX output current, per pin OUT T Storage temperature STG T Ambient temperature AMB T Junction temperature J Table 15. EP910 & EP910I Device Recommended Operating Conditions Symbol Parameter V Supply voltage CC V Input voltage I V Output voltage O T Operating temperature A t Input rise time ...
Page 27
... This parameter does not apply to EP910I devices. (10) When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic transitions occur for 75 ns after the last transition ...
Page 28
... Array clock to output delay ACO1 t Array clock minimum clock period ACNT f Maximum internal array clock ACNT frequency 772 Tables 19 and 20 show the timing parameters for EP910 devices. Notes (1), (2) Conditions EP910-30 Min Max Min Max Min Max 30 33 30.0 ( ...
Page 29
... Table 20. EP910 Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Logic array delay LAD t Output buffer and pad delay OD t Output buffer enable delay ZX t Output buffer disable delay XZ t Register setup time ...
Page 30
... ACO1 t Array clock minimum clock period ACNT f Maximum internal array clock ACNT frequency 774 Tables 21 and 22 show the timing parameters for EP910I devices. Notes (1), (2) Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo Min Max Min Max Min Max ...
Page 31
... Table 22. EP910I Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Logic array delay LAD t Output buffer and pad delay OD t Output buffer enable delay ZX t Output buffer disable delay XZ t Register setup time ...
Page 32
Notes: ...
Page 33
Features Figure 15. EP1810 Package Pin-Out Diagrams Package outlines not drawn to scale. See Windows in ceramic packages only Bottom View 68-Pin PGA ...
Page 34
Classic EPLD Family Data Sheet General Description 778 Altera EP1810 devices offer LSI density, TTL-equivalent speed, and low- power consumption. EP1810 devices have 48 macrocells, 16 dedicated input pins, and 48 I/O pins (see into four quadrants, each containing 12 ...
Page 35
Figure 16. EP1810 Block Diagram Pin numbers are for J-lead packages. Pin numbers in parentheses are for PGA packages. Quadrant A (F1) 2 Macrocell 1 (G2) 3 Macrocell 2 (G1) 4 Macrocell 3 5 (H2) Macrocell 4 6 (H1) Macrocell ...
Page 36
Classic EPLD Family Data Sheet Figure 18. Output Drive Characteristics of EP1810 Devices Drive characteristics may exceed shown curves EP1810-20 & EP1810-25 EPLDs 200 150 Typical I O Output 100 Current (mA 780 Figure 17 shows ...
Page 37
Operating Conditions Table 23. EP1810 Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage ground current MAX output current, per pin OUT T Storage temperature STG T ...
Page 38
Classic EPLD Family Data Sheet Table 26. EP1810 Device Capacitance Symbol Parameter C Input pin capacitance IN C I/O pin capacitance pin capacitance CLK1 CLK1 C C pin capacitance CLK2 CLK2 Table 27. EP1810 Device I CC ...
Page 39
Table 28. EP1810-20 & EP1810-25 External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered output PD2 t Global clock setup time SU t Global clock hold time H t Global clock high time ...
Page 40
Classic EPLD Family Data Sheet Table 30. EP1810-35 & EP1810-45 External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered output PD2 t Global clock setup time SU t Global clock hold time H ...
Page 41
Notes to tables: (1) These values are specified in (2) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (3) Measured with a device programmed as four 12-bit counters. (4) Sample-tested only. This ...
Page 42
Notes: ...