HY5PS1G1631AFP HYNIX [Hynix Semiconductor], HY5PS1G1631AFP Datasheet
HY5PS1G1631AFP
Related parts for HY5PS1G1631AFP
HY5PS1G1631AFP Summary of contents
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DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Oct. 2007 HY5PS1G431A(L)FP ...
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Revision Details Rev. 0.1 Initial data sheet released 0.2 Typo corrected 0.3 Leakage current spec added and IDD value updated 0.4 Removed improper note in ODT DC spec 0.5 Added tDS/tDH(single ended strobe) parameter 0.6 Inserted Pin Description & Adjusted ...
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Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & ...
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Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD=1.8V +/- 0.1V • VDDQ=1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data ...
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Pin Configuration & Address Table 256Mx4 DDR2 Pin Configuration 1 NC VDD NC VSSQ VDDQ DQ1 NC VSSQ VDDL VREF CKE BA2 BA0 A10 VSS VDD A12 NC ROW AND COLUMN ADDRESS TABLE Bank Address Auto Precharge Flag Row ...
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DDR2 PIN CONFIGURATION 1 NC VDD NU/RDQS DQ6 VSSQ VDDQ DQ1 DQ4 VSSQ VDDL VREF CKE BA2 BA0 A10 VSS VDD A12 NC ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag Row Address ...
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DDR2 PIN CONFIGURATION 1 NC VDD DQ14 VSSQ VDDQ DQ12 VSSQ VDD DQ6 VSSQ VDDQ DQ4 VSSQ VDDL NC, BA2 A10/AP VSS VDD NC ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag Row ...
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PIN DESCRIPTION PIN TYPE CK, CK Input CKE Input CS Input Input ODT RAS, CAS, WE Input DM Input (LDM, UDM) BA0 - BA2 Input A0 -A15 Input DQ Input/Output DQS, (DQS) (UDQS),(UDQS) Input/Output (LDQS),(LDQS) (RDQS),(RDQS) Rev. 0.7 / ...
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PIN TYPE NC V Supply DDQ VSSQ Supply V Supply DDL V Supply SSDL VDD Supply V Supply SS V Supply REF Rev. 0.7 / Oct. 2007 No Connect : No internal electrical connection is present. DQ Ground DQ Power ...
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Maximum DC Ratings 2.1 Absolute Maximum DC Ratings Symbol Parameter VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss V V Voltage on any ...
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AC & DC Operating Conditions 3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions (SSTL_1.8) Symbol Parameter VDD Supply Voltage VDDL Supply Voltage for DLL VDDQ Supply Voltage for Output VREF Input Reference Voltage VTT Termination Voltage Note: 1. ...
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DC & AC Logic Input Levels 3.2.1 Input DC Logic Level Symbol Parameter V (dc) dc input logic high IH V (dc) dc input logic low IL 3.2.2 Input AC Logic Level Symbol Parameter V (ac) ac input logic ...
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Differential Input AC logic Level Symbol Parameter V (ac) ac differential input voltage ID V (ac) ac differential cross point voltage IX Note: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, ...
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Output Buffer Characteristics 3.3.1 Output AC Test Conditions Symbol Parameter V Output Timing Measurement Reference Level OTR Note: 1. The VDDQ of the device under test is referenced. 3.3.2 Output DC Current Drive Symbol I Output Minimum Source DC ...
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OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note : 1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V) 2. Impedance measurement condition ...
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IDD Specifications & Test Conditions IDD Specifications(max) DDR2 400 Symbol x4 x8 IDD0 80 80 IDD1 95 95 IDD2P 10 10 IDD2Q 25 25 IDD2N IDD3P IDD3N 60 60 IDD4W 150 ...
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IDD Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1-5) Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RAS IDD0 min(IDD) ; ...
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Note : 1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V (exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade) 2. IDD specifications are tested after the device is properly ...
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For purposes of IDD testing, the following parameters are to be utilized Parameter CL(IDD) t RCD(IDD) t RC(IDD) t RRD(IDD)-x4/x8 t RRD(IDD)-x16 t CK(IDD) t RASmin(IDD) t RASmax(IDD) t RP(IDD) t RFC(IDD)-256Mb t RFC(IDD)-512Mb t RFC(IDD)-1Gb t RFC(IDD)-2Gb Detailed IDD7 ...
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Input/Output Capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, ...
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Timing Parameters by Speed Grade Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time(differential strobe) DQ and ...
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Parameter Four Active Window for 1KB page size products Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read ...
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Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time DQ and DM input hold time Control & ...
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Parameter Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to ...
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General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For ...
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Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
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Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used ...
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Fig. a. Illustration of nominal slew rate for tIS,tDS CK,DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF V (dc)max IL V (ac)max IL Vss Delta TF Setup Slew Rate V = Falling Signal Rev. ...
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Fig. b. Illustration of tangent line for tIS,tDS CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF V (dc)max IL V (ac)max IL Nomial line Vss Delta TF Setup Slew Rate Tangent line[V = ...
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Fig. c. Illustration of nominal line for tIH, tDH CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min region V (dc) REF V (dc)max IL V (ac)max IL Vss Hold Slew Rate V = ...
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Fig. d. Illustration of tangent line for tIH , tDH CK, DQS CK, DQS V DDQ V (ac)min IH V (dc)min IH V (dc) REF REF region V (dc)max IL V (ac)max IL Vss Tangent line[V Hold ...
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Command / 0.8 -25 Address Slew 0.7 -43 rate(V/ns) 0.6 -67 0.5 -100 ...
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The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( t CL, t CH) refers to ...
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Below figure shows a method to calcu- late these ...
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Package Dimensions Package Dimension(x4,x8) 68Ball Fine Pitch Ball Grid Array Outline A1 BALL MARK < Top View> 68X Φ0.45 ± ...
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Package Dimension(x16) 92Ball Fine Pitch Ball Grid Array Outline A1 BALL MARK < Top View> 68X ...