BC41B143A-ds-001Pe CSR, BC41B143A-ds-001Pe Datasheet
BC41B143A-ds-001Pe
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BC41B143A-ds-001Pe Summary of contents
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... Intel WCS activity and channel signalling. PCM Production Information © Cambridge Silicon Radio Limited 2005 » QJolj ® v2.0 System with EDR Production Data Sheet for BC41B143A July 2005 Page 1 of 102 ...
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... RF Transmitter....................................................................................................................................... 38 7.2.1 IQ Modulator .............................................................................................................................. 38 7.2.2 Power Amplifier .......................................................................................................................... 38 7.2.3 Auxiliary DAC ............................................................................................................................. 38 7.3 RF Synthesiser ...................................................................................................................................... 38 7.4 Power Control and Regulation............................................................................................................... 38 7.5 Clock Input and Generation ................................................................................................................... 39 7.6 Baseband and Logic .............................................................................................................................. 39 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Status Information Page 2 of 102 ...
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... Current Consumption in UART Bypass Mode ............................................................................ 65 10.5 USB Interface ........................................................................................................................................ 66 10.5.1 USB Data Connections .............................................................................................................. 66 10.5.2 USB Pull-Up Resistor................................................................................................................. 66 10.5.3 Power Supply ............................................................................................................................. 66 10.5.4 Self Powered Mode.................................................................................................................... 67 10.5.5 Bus Powered Mode.................................................................................................................... 68 10.5.6 Suspend Current ........................................................................................................................ 69 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Status Information Page 3 of 102 ...
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... Dry Pack Information ............................................................................................................................. 96 15.4 Baking Conditions.................................................................................................................................. 97 15.5 Product Information ............................................................................................................................... 97 16 Contact Information ..................................................................................................................................... 98 17 Document References ................................................................................................................................. 99 Terms and Definitions ...................................................................................................................................... 100 Document History ............................................................................................................................................. 102 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Status Information Page 4 of 102 ...
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... Figure 14.1: BlueCore4-ROM 84-Ball VFBGA Package Dimensions.................................................................... 89 Figure 15.1: Typical Lead-Free Re-flow Solder Profile.......................................................................................... 90 Figure 17.1: Tape and Reel Orientation ................................................................................................................ 93 Figure 17.2: Tape Dimensions .............................................................................................................................. 94 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Status Information Page 5 of 102 ...
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... Equation 10.9: Baud Rate ..................................................................................................................................... 64 Equation 10.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz clock ........................ 81 Equation 10.11: PCM_SYNC Frequency Relative to PCM_CLK........................................................................... 81 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Status Information Page 6 of 102 ...
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... While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. CSR’s products are not authorised for use in life-support or safety-critical applications This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Status Information ...
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... Power management includes digital shut down, wake up commands with an integrated low power oscillator for ultra-low power Park/Sniff/Hold mode ! ‘Clock request’ output to control an external clock This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Auxiliary Features (continued) ! On-chip linear regulator; 1.8V output from a 2.2 - 4.2V input ! ...
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... Figure 2.1: BlueCore4-ROM Device Pinout This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 6 x 6mm VFBGA Package Information Orientation from top of device ...
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... G10 internal pull-down Bi-directional with weak PCM_CLK H10 internal pull-down This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 6 x 6mm VFBGA Package Information Description Single-ended receiver input Control output for external TX/RX switch (if fitted) Control output for external PA (if fitted) Transmitter output/switched receiver input ...
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... AIO[1] H5 Bi-directional AIO[2] J5 Bi-directional This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 6 x 6mm VFBGA Package Information Description Reset if high. Input debounced, so must be high for >5ms to cause a reset Reset if low. Input debounced, so must be low for >5ms to cause a reset Chip select for Serial Peripheral Interface, ...
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... BlueCore2-ROM that has no regulator enable pin. (2) Positive supply for PIO[3:0] and PIO[11:8] (3) Positive supply for SPI/PCM ports and PIO[7:4] This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 6 x 6mm VFBGA Package Information Pad Type Description Linear regulator input Linear regulator voltage input ...
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... Supply Voltage: VREG_IN Note: (1) Typical figures are given for RF performance between -40°C and +105°C (2) The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is not guaranteed above 4.2V This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Min -40°C -0.4V -0.4V -0.4V VSS-0.4V Min -40° ...
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... VDD_ANA. (6) Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to damage the rest of BlueCore4, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.2V. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Min Typ 1.70 1.78 -250 ...
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... Input leakage current (1) VSS_PADS < V < VDD_USB IN C Input capacitance I Output Voltage levels to correctly terminated USB Cable V output logic level low OL V output logic level high OH This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Min Typ -0.4 -0.4 0.7VDD - - VDD-0.2 VDD-0.4 -100 +10 +40 -5.0 -1.0 +0.2 +1 ...
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... Output Voltage Voltage range (I =0mA) O Current range Minimum output voltage (I =100μA) O Maximum output voltage (I =10mA) O High Impedance leakage current Offset (3) Integral non-linearity Settling time (50pF load) This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Min Typ 1.40 1.50 1.50 1.60 0.05 0.10 Min Typ - - ...
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... CDMA/3G TCXO frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz (8) Clock input can either be sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Min Typ 8.0 5.0 6 ...
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... Low power mode on the linear regulator is entered and exited automatically when the chip enters/leaves Deep Sleep mode. For more information about the electrical characteristics of the linear regulator, see section 3 in this document. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Connection UART Rate Type ...
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... Up to three exceptions are allowed in v2.0 + EDR of the Bluetooth specification. BlueCore4-ROM is guaranteed to meet the ACP performance as specified by the Bluetooth specification v2.0 + EDR. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = +20°C Min Typ Max - 4 ...
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... Integrated in 1MHz bandwidth and then normalised to a 1Hz bandwidth. (4) Integrated in 30kHz bandwidth and then normalised to a 1Hz bandwidth. (5) Integrated in 5MHz bandwidth and then normalised to a 1Hz bandwidth. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = +20°C (Continued) Min Typ Max ...
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... Measured at the unbalanced port of the balun. Integrated in 100kHz bandwidth and then normalized to 1Hz. Actual figure is typically below -160dBm/Hz except for peaks of -65dBm at 1600MHz, -54dBm inband at 2.4GHz and -65dBm at 3.2GHz. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = +20°C Frequency ...
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... BER) measured at 1.850 – 1.910 the unbalanced port of the balun. 1.850 – 1.910 1.920 – 1.980 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = +20°C (Continued) Min Typ Max - 0 - ...
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... Up to three exceptions are allowed in v2.0 + EDR of the Bluetooth specification 4.2.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = -40°C Min Typ - 5 ...
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... Up to three exceptions are allowed in v2.0 + EDR of the Bluetooth specification 4.3.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = -25°C Min Typ - 5 ...
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... Up to three exceptions are allowed in v2.0 + EDR of the Bluetooth specification 4.4.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = +85°C Min Typ - 2 ...
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... Up to three exceptions are allowed in v2.0 + EDR of the Bluetooth specification. 4.5.2 Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Basic Data Rate Temperature = +105°C Min Typ - 0 ...
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... 3MHz o EDR Differential Phase Encoding Notes: (1) BlueCore4-ROM firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = +20°C Min Typ Max Specification - 1.5 ...
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... Up to five exceptions are allowed in EDR RF Test Specification v2.0.E.2. BlueCore4-ROM is guaranteed to meet the C/I performance as specified by the EDR RF Test Specification v2.0.E.2. (3) Measured 2405MHz, 2441MHz, 2477MHz 0 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = +20°C Min Typ Max - ...
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... BlueCore4-ROM firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. (2) Class 2 RF transmit power range, Bluetooth v2.0 + EDR specification. (3) Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = -40°C Min Typ Max - ...
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... DQPSK (1) Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = -40°C Min Typ Max - -89 8DPSK - -79 ...
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... BlueCore4-ROM firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. (2) Class 2 RF transmit power range, Bluetooth v2.0 + EDR specification. (3) Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = -25°C Min Typ Max - ...
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... DQPSK (1) Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = -25°C Min Typ Max - -85 8DPSK - -79 ...
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... Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2. (4) Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = +85°C Min Typ ...
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... DQPSK (1) Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = +85°C Min Typ Max - -85 8DPSK - -74 ...
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... BlueCore4-ROM firmware maintains the transmit power to be within the Bluetooth v2.0 + EDR specification limits. (2) Class 2 RF transmit power range, Bluetooth v2.0 + EDR specification. (3) Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = +105°C Min Typ Max - ...
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... Sensitivity at 0.01% BER π/4 DQPSK Maximum received signal at (1) 0.1% BER Notes: (1) Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Radio Characteristics – Enhanced Data Rate Temperature = +105°C Min Typ Max - -85 8DPSK ...
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... RESET RESETB VDD_ PADS VDD_ CORE VDD _ RADIO XTAL_ OUT XTAL_ IN Figure 6.1: BlueCore4-ROM Device Diagram This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Power Control and Regulation VREG In Out Production Information © Cambridge Silicon Radio Limited 2005 Device Diagram AIO[0] ...
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... Bluetooth specification v2.0 + EDR. 7.4 Power Control and Regulation BlueCore4-ROM contains a 1.8V linear regulator which can be used to power the complete chip. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Description of Functional Blocks Page 38 of 102 ...
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... Bluetooth stack. 7.6.5 ROM 4Mbits of metal programmable ROM is provided for system firmware implementation. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Description of Functional Blocks Page 39 of 102 ...
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... The features are configured in firmware. Since the details of some methods are proprietary (e.g. Intel WCS) please contact CSR for details. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Description of Functional Blocks ...
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... UART In the implementation shown in Figure 8.1 the internal processor runs the Bluetooth stack up to the Host Controller Interface (HCI). The Host processor must provide all upper layers including the application. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe HCI LM LC Baseband ...
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... Broadcast ! Channel quality driven data rate ! All standard Bluetooth Test Modes ! Standard firmware upgrade via USB (DFU) This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 CSR Bluetooth Software Stacks Page 42 of 102 ...
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... SCO channels are normally routed via HCI (over BCSP). However three SCO channels can be routed over the chip’s single PCM port (at the same time as routing any remaining SCO channels over HCI). This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe http://www.csr.com Production Information © Cambridge Silicon Radio Limited 2005 ...
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... In the version of the firmware, shown in Figure 8.2 the upper layers of the Bluetooth stack up to RFCOMM are run on-chip. This reduces host-side software and hardware requirements at the expense of some of the power and flexibility of the HCI only stack. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe RFCOMM SDP L2CAP ...
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... CQDDR increases the effective data rate in noisy environments. ! RSSI used to minimise interference to other radio devices using the ISM band. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 CSR Bluetooth Software Stacks Page 45 of 102 ...
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... BlueLab is supplied with example code including a full implementation of the headset profile. Note: Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe VM Application Software RFCOMM SDP L2CAP ...
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... CSR’s BlueLab and Casira development kits are available to allow the evaluation of the BlueCore4-ROM hardware and software, and as toolkits for developing on-chip and host software. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Consequently, the efficiency is maximised. ! The differential encoding also allows for demodulation without the knowledge of an absolute value for the phase of the RF carrier. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe (1) data rates with minimal disruption to Bits Per Symbol 1 ...
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... Figure 9.3 illustrates the 8DPSK constellation and Table 9.3 defines the phase encoding. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © ...
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... Table 9.3: 3-Bits Determine Phase Shift Between Consecutive Symbols This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 011 001 100 101 Production Information © Cambridge Silicon Radio Limited 2005 Enhanced Data Rate 000 Phase Shift 0 π ...
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... Starting from the substrate (chip side), the outputs can each be modelled as an ideal current source in parallel with a lossy resistance and a capacitor. The bond wire can be represented as series inductance LNA _ Figure 10.1: Circuit TX/RX_A and TX/RX_B This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe RF Switch R2 10 0.9pF RF Switch R3 10 ...
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... BlueCore4-ROM enables the external PA only when transmitting. Before transmitting, the chip normally ramps up the power to the internal PA, then it ramps it down again afterwards. However suitable external PA is used, it may be possible to ramp the power externally by driving the TX_PWR pin on the PA from AUX_DAC. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe BlueCore4-ROM L1 1.5nH ...
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... Table 10.1: TXRX_PIO_CONTROL Values This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe carrier AUX_DAC Use PIO[0], PIO[1], AUX_DAC not used to control RF. Power ramping is internal. PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC not used. Power ramping is internal. PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set gain of external PA ...
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... This is to guarantee that the firmware can maintain timing accuracy in accordance with the Bluetooth v2.0 specification. Radio activity may occur after 11ms, therefore at this point, the timing accuracy of the external clock source must be within 20ppm. CLK_REQ 0 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Min 7.5MHz 20:80 - 400mV pk-pk ...
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... Actual Allowable Clock Presence Delay on XTAL_IN vs. PSKey Setting 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0 5.0 Figure 10.5: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 10.0 15.0 20.0 PSKEY_CLOCK_STARTUP_DELAY Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions 25.0 30.0 Page 55 of 102 ...
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... Default Table 10.3: PS Key Values for CDMA/3G Phone TCXO Frequencies This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe PSKEY_ANA_FREQ (0x1fe) (Units of 1kHz) Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions 7680 14400 15360 16200 16800 19200 ...
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... The resonant frequency may be trimmed with the crystal load capacitance. BlueCore4-ROM contains variable internal capacitors to provide a fine trim. The BlueCore4-ROM driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe ...
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... This leaves a margin of ±15ppm for frequency drift with ageing and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is required. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe and C . The remainder should be from the external trim int for best noise performance ...
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... The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the oscillator. Min Frequency 8MHz Initial Tolerance - Pullability - Table 10.4: Oscillator Negative Resistance 10.3.6 Crystal PS Key Settings See tables in Section 10.2.5. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe ( )( ) + + trim ...
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... Conditions 3.4pF centre value trim Crystal C = 2pF o Transconductance setting = 2mA/V Loop gain = This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 5.5 6.5 7.5 8.5 Load Capacitance (pF) 16 MHz 28 MHz Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions 9.5 10.5 11.5 12.5 Page 60 of 102 ...
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... Gm Typical Gm Minimum Gm Maximum Figure 10.9: Crystal Driver Transconductance vs. Driver Level Register Setting Note: Drive level is set by Persistent Store Key PSKEY_XTAL_LVL (0x241). This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe BlueCore4-ROM XTAL Driver Characteristics PSKEY_XTAL_LVL Production Information © ...
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... 5pF (3.9pF plus 1.1 pF stray (Crystal total load capacitance 8.5pF) Note: This is for a specific crystal and load capacitance. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Negative Resistance for 16 MHz Xtal 6.0 7.0 8.0 9.0 10.0 11.0 Drive Level Setting Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions 12 ...
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... Parameter Minimum Baud Rate Maximum Flow Control Parity Number of Stop Bits Bits per channel Table 10.5: Possible UART Settings This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe (1) . BlueCore4-ROM UART_TX UART_RX UART_RTS UART_CTS Possible Values 1200 Baud (≤2%Error) 9600 Baud (≤1%Error) 1.5Mbaud (≤ ...
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... Note: (1) Table will be extended to cover EDR This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe t BRK Figure 10.12: Break Signal PSKEY_UART _BAUD_RATE = Rate . 0 004096 Equation 10.9: Baud Rate Persistent Store Value Hex Dec ...
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... For BlueCore3-Multimedia the standard UART is supplied by VDD_USB so has signalling levels of 0V and VDD_USB. Whereas in the UART bypass mode the signals appear on the PIO[4:7] which are supplied by VDD_PADS, therefore the signalling levels are 0V and VDD_PADS. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe RESET UART_TX PIO4 ...
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... The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet the USB specification, the voltage on the VDD_USB supply terminals must be an absolute minimum of 3.1V. CSR recommends 3.3V for optimal USB signal quality. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions ...
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... The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding pin number. Note: USB_ON is shared with BlueCore4-ROM PIO terminals Identifier vb1 R vb2 Table 10.7: USB Interface Component Values This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe PIO 1.5KΩ USB_DP USB_DN D- R vb1 ...
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... Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore4-ROM will result in reduced receive sensitivity and a distorted RF transmit signal. BlueCore4-ROM Figure 10.15: USB Connections for Bus Powered Mode This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe R s USB_DP D+ R ...
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... Figure 10.16: USB_DETACH and USB_WAKE_UP Signal 10.5.8 USB Driver A USB Bluetooth device driver is required to provide a software interface between BlueCore4-ROM and Bluetooth software running on the host computer. Suitable drivers are available from www.csrsupport.com. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 10ms max No max Disconnected Production Information © ...
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... To invoke auto increment, SPI_CSB is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Hold SPI_CSB high for two SPI_CLK cycles Take SPI_CSB low and clock in the ...
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... BlueCore4-ROM should not be connected in a multi slave arrangement by simple parallel connection of slave MISO lines. When BlueCore4-ROM is deselected (SPI_CSB = 1), the SPI_MISO line does not float, instead, BlueCore4-ROM outputs 0 if the processor is running stopped. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Address(A) Data(A) Data(A+1) ...
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... BlueCore4-ROM is also compatible with the Motorola SSI™ interface Note: (1) Subject to firmware support, contact CSR for current status. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions (1) . Page 72 of 102 ...
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... When configured as the Master of the PCM interface, BlueCore4-ROM generates PCM_CLK and PCM_SYNC. BlueCore4-ROM Figure 10.19: BlueCore4-ROM as PCM Interface Master When configured as the Slave of the PCM interface, BlueCore4-ROM accepts PCM_CLK rates up to 2048kHz. BlueCore4-ROM Figure 10.20: BlueCore4-ROM as PCM Interface Slave This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe PCM_OUT PCM_IN PCM_CLK 128/256/512kHz PCM_SYNC 8kHz ...
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... As with Long Frame Sync, BlueCore4-ROM samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe ...
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... PCM_IN The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With BlueCore4-ROM in Slave mode, the frequency of PCM_CLK can 4.096MHz. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe ...
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... Figure 10.25: 16-Bit Slot Length and Sample Formats 10.7.7 Additional Features BlueCore4-ROM has a mute facility that forces PCM_OUT Master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Sign ...
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... Hold time for PCM_CLK low to PCM_IN invalid hpinclkl Note: (1) Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are reduced. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Min 4MHz DDS generation. Selection of frequency is - programmable, see Table 10.11 48MHz DDS generation ...
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... PCM_CLK t PCM_OUT t PCM_IN Figure 10.26: PCM Master Timing Long Frame Sync t dmclksynch PCM_SYNC PCM_CLK PCM_OUT PCM_IN Figure 10.27: PCM Master Timing Short Frame Sync This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe dmclksynch f mlk t t mclkh mclkl t ,t dmclkpout r f MSB (LSB) ...
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... Set-up time for PCM_IN valid to CLK low supinsclkl t Hold time for PCM_CLK low to PCM_IN invalid hpinsclkl This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Table 10.10: PCM Slave Timing Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions Min ...
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... PCM_IN MSB (LSB) Figure 10.28: PCM Slave Timing Long Frame Sync PCM_CLK t t susclksynch hsclksynch PCM_SYNC PCM_OUT PCM_IN Figure 10.29: PCM Slave Timing Short Frame Sync This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe f sclk t tsclkl t susclksynch t dsclkhpout LSB (MSB) t hpinsclkl f sclk ...
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... The frequency of PCM_SYNC relative to PCM_CLK can be set using following equation: Equation 10.11: PCM_SYNC Frequency Relative to PCM_CLK CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe CNT _ RATE = × ...
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... MUTE_EN 48M_PCM_CLK_GEN_EN LONG_LENGTH_SYNC_EN - MASTER_CLK_RATE ACTIVE_SLOT SAMPLE_FORMAT Table 10.11: PSKEY_PCM_CONFIG32 Description This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Bit Position Description 0 Set selects Master mode with internal generation of PCM_CLK and PCM_SYNC. 1 selects Slave mode requiring externally generated PCM_CLK and PCM_SYNC ...
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... PIO Defaults for BTv2.0 + EDR HCI Level Bluetooth Stack CSR cannot guarantee that these terminal functions remain the same. Please refer to the software release note for the implementation of these PIO lines, as they are firmware build specific. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Bit Position Description [12:0] Sets PCM_CLK counter limit ...
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... PIO[2] can be used as the OR output with the TCXO enable signal from BlueCore4-ROM. VDD TCXO Enable Figure 10.31: Example TXCO Enable OR Function This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 2 C interface. The interface is formed using software to drive these lines EEPROMS for use with BlueCore. This +1.8V 10nF 2.2KΩ ...
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... BlueCore4-ROM is configured for the actual XTAL_IN frequency clock is present at XTAL_IN, the oscillator in BlueCore4-ROM free runs, again at a safe frequency. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Note: (1) Cold Reset constitutes one of the following: ! Power cycle ! System reset (firmware fault code) ! Reset signal, see Section 10.11. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Device Terminal Descriptions Page 86 of 102 ...
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... The regulator enable pin, VREG_EN, can be used to enable and disable the BlueCore4-ROM device if one of the on-chip regulators is being used. The pin is active high, and has a weak pull-up to the active regulator input. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Application Schematic Figure 11.1: Application Circuit for Radio Characteristics Specification with 6 x 6mm VFBGA Package This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Application Schematic Page 88 of 102 ...
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... Package Dimensions 12 6mm VFBGA 84-Ball Package Figure 12.1: BlueCore4-ROM 84-Ball VFBGA Package Dimensions This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Package Dimensions Page 89 of 102 ...
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... Figure 13.1: Typical Lead-Free Re-flow Solder Profile This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Table 13.1: Soldering Profile Zones Lead Free Reflow Solder Profile 2 200 250 300 Time (s) Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Device absolute maximum reflow temperature: 260°C Devices will withstand the specified profile. Lead-free devices will withstand up to three reflows to a maximum temperature of 260°C. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Solder Profiles ...
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... Type 84-Ball VFBGA UART and USB (Pb free) Minimum Order Quantity 2kpcs Taped and Reeled This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Package Size Shipment Method 6 x 6mm x 1mm Tape and reel Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Tape Orientation and Dimensions The general orientation of the BGA in the tape is as shown in Figure 15.1. User Direction of Feed Figure 15.1: Tape and Reel Orientation This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe BGA Production Information © Cambridge Silicon Radio Limited 2005 Tape and Reel Information ...
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... P1) is ±0.1mm. The reel is made of high impact injection moulded polystyrene. The carrier tape is made of polystyrene with carbon. The cover tape is made of antistatic polyester film and an antistatic heat activated adhesive coating. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 4.0 0.25 •See Note 1 Ø ...
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... Tape Width B Min C 16mm 1.5mm 13.0+0.5/-0.2mm Tape Size 16mm Table 15.2: Diameter Dependent Dimensions This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Access Hole at Slot Location ∅ min (Arbor hole diameter) If present, tape slot in core for tape start: 2.5mm min. ...
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... RH for a minimum of one year as long as the dry-pack bag has not become punctured. Humidity indicators inside the dry-pack bag will confirm this when the bag is opened. This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Humidity Indicator Card 10% ~ 30% Desiccant: two units bags each containing 2 units of desiccant ...
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... Product Information Example product information labels are shown is Figure 15.5. Figure 15.5: Product Information Labels A product information label is placed on each reel, primary package and shipment package This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe 4 ROM Production Information © Cambridge Silicon Radio Limited 2005 ...
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... Seoul 137-863 Korea Tel: +82 31 389 0541 Fax : +82 31 389 0545 e-mail: sales@csr.com To contact a CSR representative This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe CSR Denmark Novi Science Park Niels Jernes Vej 10 9220 Aalborg East Denmark Tel: +45 72 200 380 Fax: +45 96 354 599 e-mail: sales@csr ...
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... Specification of the Bluetooth System Universal Serial Bus Specification 2 Selection EEPROMS for Use with BlueCore RF Test Specification v2.0.E.2 This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Reference, Date: v1.2, 05 November 2003 V2.0 + EDR, 04 November 2004 v2.0, 27 April 2000 bcore-an-008Pb, 30 September 2003 v2.0.E.2, 04 November 2004 Production Information © ...
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... Logical Link Control and Adaptation Protocol (protocol layer) LC Link Controller LCD Liquid Crystal Display LFBGA Low profile Fine Ball Grid Array LNA Low Noise Amplifier This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Terms and Definitions Page 100 of 102 ...
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... Voltage Controlled Oscillator VM Virtual Machine W-CDMA Wideband Code Division Multiple Access WEB Write Enable (Active Low) www world wide web This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe Production Information © Cambridge Silicon Radio Limited 2005 Terms and Definitions Page 101 of 102 ...
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... Typical Radio Performance – Basic Data Rate section added ! Application Schematic added BlueCore™4-ROM Product Data Book BC41B143A-db-001Pe This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-001Pe July 2005 Production Information © Cambridge Silicon Radio Limited 2005 Document History Page 102 of 102 ...