AX88772 ASIX [ASIX Electronics Corporation], AX88772 Datasheet - Page 7

• Manufacturer Part Number: AX88772
• Description: USB to 10/100 Fast Ethernet/HomePNA Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

CRS
TX_CLK
TXD [3:0]
TX_EN
TX_ER
EECK
EECS
EEDI
EEDO
XIN25M
XOUT25M
RSTPB
RXIP
RXIN
TXOP
TXON
IBREF
RX_LED
COL_LED
LINK_LED
FDX_LED
ET_SPEED_LED
I5/PD
O3
O3
O3
O3
O2
O2
O2
O5
O5
O5
O3
O3
I2
I2
I3
O
O
B
I
I
I
82, 83, 84,
115
102
85
89
88
59
58
65
52
51
62
61
56
92
93
94
95
96
4
5
6
9
USB to 10/100 Fast Ethernet/HomePNA Controller
Serial EEPROM Interface
Carrier Sense. CRS is asserted high asynchronously by the PHY when
either transmit or receive medium is non-idle.
Transmit Clock. TX_CLK is received from PHY to provide timing
reference for the transfer of TXD [3:0], TX_EN and TX_ER signals
on transmit direction of MII interface.
Transmit Data. TXD [3:0] is transitioned synchronously with respect
to the rising edge of TX_CLK.
Transmit Enable. TX_EN is transitioned synchronously with respect
to the rising edge of TX_CLK. TX_EN is asserted high to indicate a
valid TXD [3:0].
Transmit Coding Error. TX_ER is transitioned synchronously with
respect to the rising edge of TX_CLK. When asserted high for one or
more TX_CLK, the PHY shall emit one or more code-groups that are
not part of the valid data or delimiter set somewhere in the frame
being transmitted.
EEPROM Clock. EECK is an output clock to EEPROM to provide
timing reference for the transfer of EECS, EEDI, and EEDO signals.
EEPROM Chip Select. EECS is asserted high synchronously with
respect to rising edge of EECK as chip select signal.
EEPROM Data In. EEDI is the serial output data to EEPROM’s data
input pin and is synchronous with respect to the rising edge of EECK.
EEPROM Data Out. EEDO is the serial input data from EEPROM’s
data output pin.
25Mhz crystal or oscillator clock input. This clock is needed for the
embedded 10/100 Ethernet PHY to operate.
25Mhz crystal or oscillator clock input.
Reset input of embedded Ethernet PHY: RSTPB is an active low input
used for resetting internal Ethernet PHY. When internal Ethernet
PHY is used, user can connect this pin to an external RC circuit,
which gets pulled-up to AVDDK (2.5V). The reset period from 50ms
to 150ms is recommended.
Receive data input positive pin for both 10BASE-T and
100BASE-TX.
Receive data input negative pin for both 10BASE-T and
100BASE-TX.
Transmit data output positive pin for both 10BASE-T and 100
BASE-TX
Transmit data output negative pin for both 10BASE-T and 100
BASE-TX
For Ethernet PHY’s internal biasing. Please connect to GND through
a 12.3Kohm resistor.
Receive activity LED indicator. This pin drives low and high in turn
(blinking) when Ethernet PHY is receiving and drives high when not
receiving.
Collision detected LED indicator. This pin drives low when the
Ethernet PHY detects collision and drives high when no collision.
Link status LED indicator. This pin drives low continuously when the
Ethernet link is up and drives low and high in turn (blinking) when
Ethernet PHY is in receiving or transmitting state.
Full-Duplex LED indicator. This pin drives low when the Ethernet
PHY is in full-duplex mode and drives high when in half duplex
mode.
Ethernet speed LED indicator. This pin drives low when the Ethernet
PHY is in 100BASE-TX mode and drives high when in 10BASE-T
mode.
Ethernet Phy Interface
Misc. Pins
7
ASIX ELECTRONICS CORPORATION
AX88772