AX88772 ASIX [ASIX Electronics Corporation], AX88772 Datasheet - Page 8

• Manufacturer Part Number: AX88772
• Description: USB to 10/100 Fast Ethernet/HomePNA Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

RESET_N
EXTWAKEUP_N I5/PU/S
GPIO [2:0]
PHYRST_N
FORCEFS_N
LED
USB_SPEED_LE
D
TESTSPEEDUP
HS_TEST_MODE I3/PD
SCAN_TEST
SCAN_ENABLE
CLK60EXT
CLKSEL
DB [4:0]
INT_REGULATO
R_EN
VDDAH
GNDAH
V25
VDDK
VDD2
VDD3
GND
AVDDK
AVDD3
I5/PU/S
B5/PD
I3/PU
I3/PD
I3/PD
I3/PD
I3/PD
I3/PD
O2
O3
O3
I2
P
P
P
P
P
P
P
P
P
I
80, 86, 123 Digital I/O Power. 2.5V.
16, 24, 74,
25, 40, 75,
81, 87, 98,
49, 53, 57,
64, 66, 68
28, 37, 39 Analog I/O Power. 3.3V.
8, 19, 41,
7, 17, 18,
101, 111,
112, 113,
100, 119,
124, 127
99, 118
97, 128
1, 2, 3
122
125
126
114
12
15
13
42
43
44
45
46
20
22
23
21
11
USB to 10/100 Fast Ethernet/HomePNA Controller
Chip Reset Input. RESET_N pin is active low. When asserted, it puts
the entire chip into reset state immediately. After completing reset,
EEPROM data will be loaded automatically.
Remote-wakeup trigger from external pin. EXTWAKEUP_N should
be asserted low for more than 2 cycles of 12MHz clock to be
effective. For
General Purpose Input/ Output Pins. These pins are default as input
pins after power-on reset. Please use GPIO0 for controlling the power
down pin of external Ethernet Phy, if applicable.
PHYRST_N is a tri-state output used for resetting external Ethernet
PHY. This pin is default in tri-state after power-on reset. If external
Ethernet PHY’s reset level is active low, connect this to PHY’s reset
pin with a pulled-down resistor. If it’s active high, connect this to
PHY with a pulled-up resistor. This way can make sure the external
Ethernet PHY stays in reset state before software brings it out of reset.
Force USB Full Speed (active low). For normal operation, user should
keep this pin NC to enable USB High Speed handshaking process to
decide the speed of USB bus. Setting this pin low sets the device to
operate at Full speed mode only and disables Chirp K (HS
handshaking process).
LED indicator: When USB bus is in Full speed, this pin drives high
continuously. When USB bus is in High speed, this pin drives low
continuously. This pin drives high and low in turn (blinking) to
indicate TX data transfer going on whenever the host controller sends
bulk out data transfer.
USB bus speed LED indicator. When USB bus is in Full speed, this
pin drives high continuously. When USB bus is in High speed, this
pin drives low continuously.
Test pin. For normal operation, user should keep this pin NC.
Test pin. For normal operation, user should keep this pin NC.
Test pin. For normal operation, user should keep this pin NC.
Test pin. For normal operation, user should keep this pin NC.
Test pin. For normal operation, user should keep this pin NC.
Test pin. For normal operation, user should keep this pin NC.
Debug pins. For normal operation, user should set these pins low.
On-chip 3.3V to 2.5V voltage regulator enable. Connect this pin to
VDDAH directly to enable on-chip regulator. Connect this pin to
GNDAH to disable on-chip regulator.
3.3V Power supply to on-chip 3.3V to 2.5V voltage regulator.
Ground pin of on-chip 3.3V to 2.5V voltage regulator.
2.5V voltage output of on-chip 3.3V to 2.5V voltage regulator.
Digital Core Power. 2.5V.
Digital I/O Power. 3.3V.
Digital Ground.
Analog Core Power. 2.5V.
Power and Ground Pins
On-chip Regulator Pins
8
ASIX ELECTRONICS CORPORATION
AX88772