AX88772_07 ASIX [ASIX Electronics Corporation], AX88772_07 Datasheet - Page 27

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AX88772_07

Manufacturer Part Number
AX88772_07
Description
USB to 10/100 Fast Ethernet/HomePNA Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
6.2.1.23 Software Reset Register (20h, write only)
6.2.1.24 Software PHY Select Status Register (21h, read only) and Software PHY Select Register
Reserved
PRTE: External Phy Reset pin Tri-state Enable.
RR: Clear frame length error for Bulk In.
RT: Clear frame length error for Bulk Out.
PRL: External Phy Reset pin Level. When SCPR bit = 1 and PRTE = 0, this bit controls the output level of external
BZ: Force Bulk In to return a Zero-length packet.
IPRL: Internal Phy Reset control. When SCPR bit = 1, this bit acts as reset signal of internal Ethernet Phy.
IPPD: Internal Ethernet Phy Power Down control.
1: Set to high (default).
1: Internal Ethernet Phy is in operating state.
1: Internal Ethernet Phy is in power down mode (default).
1: Enable, i.e., the external PHYRST_N pin is tri-stated (default). This allows the PHYRST_N pin’s active level to
0: Disabled, i.e., the external PHYRST_N pin’s level is driven by either PRL bit or internal “USB RESET” based on
0: Set to low.
1: Software can force Bulk In to return a zero-length USB packet.
0: Normal operation mode (default).
0: Internal Ethernet Phy in reset state (default).
0: Internal Ethernet Phy is in operating mode.
PSEL: Phy Select, when ASEL = 0 (manually select the Phy to operate)
ASEL: Auto Select or Manual Select
1: set high to clear state.
0: set low to exit clear state (default).
1: set high to enter clear state.
0: set low to exit clear state (default).
Bit7
Bit7
1: Select embedded 10/100 Ethernet Phy (default).
1: Automatically select based on link status of embedded 10/100 Ethernet Phy (default).
0: Manually select between the embedded 10/100 Ethernet Phy and the external one.
0: Select external Phy, which is attached to the MII interface
be controlled by external pulled-up (active high during power-on) or pulled-down resistor (active low during
power-on).
the setting in SCPR bit in Flag byte of EEPROM.
PHYRST_N pin.
22h, write only)
IPPD
Bit6
Bit6
IPRL
Bit5
Bit5
Reserved
USB to 10/100 Fast Ethernet/HomePNA Controller
Bit4
Bit4
BZ
PRL
Bit3
Bit3
27
PRTE
Bit2
Bit2
ASIX ELECTRONICS CORPORATION
ASEL
Bit1
Bit1
RT
PSEL
Bit0
Bit0
RR
AX88772

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