AX88780_07

Manufacturer Part NumberAX88780_07
DescriptionHigh-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
ManufacturerASIX [ASIX Electronics Corporation]
AX88780_07 datasheet
 
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High-Performance Non-PCI Single-Chip
32-bit 10/100M Fast Ethernet Controller
Features
High-performance non-PCI local bus
16/32-bit SRAM-like host interface
Support big/little endian data bus type
Large embedded SRAM for packet buffers
32K bytes for receive buffer
8K bytes for transmit buffer
Support IP/TCP/UDP checksum offloads
Support interrupt with high or low active trigger
mode
Single-chip Fast Ethernet controller
Compatible with IEEE802.3, 802.3u standards
Integrated Fast Ethernet MAC/PHY transceiver in
one chip
Support 10Mbps and 100Mbps data rate
Support full and half duplex operations
Support 10/100Mbps
N-way
operation
Support IEEE 802.3x flow control for full-duplex
operation
Product Description
The AX88780 is a high-performance and cost-effective single-chip Fast Ethernet controller for various embedded
systems including consumer electronics and home network markets that require a higher level of network connectivity.
The AX88780 supports 16/32-bit SRAM-like host interface and integrates on-chip Fast Ethernet MAC and PHY, which
is IEEE802.3 10Base-T and IEEE802.3u 100Base-T compatible. The AX88780 supports full-duplex or half-duplex
operation at 10/100Mbps speed with auto-negotiation or manual setting. The AX88780 integrates large embedded SRAM
for packet buffers to accommodate high bandwidth applications and supports IP/TCP/UDP checksum to offload
processing loading from microprocessor/microcontroller in an embedded system.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
Support back-pressure flow control for half-duplex
operation
Support packet length set by software
Support MII interface for external Ethernet PHY
and HomePNA/HomePlug PHY applications
Support Wake-on-LAN function by following events
Detection of network link-up state
Receipt of a Magic Packet
Support Magic Packet detection for remote wake-up
after power–on reset
Support EEPROM interface
Support PCMCIA in 16-bit mode
Support synchronous or asynchronous mode to host
MCU
Support LED pins for various network activity
Auto-negotiation
indications
Integrated voltage regulator from 3.3V to 2.5V
2.5V for core and 3.3V I/O with 5V tolerance
128-pin LQFP with CMOS process, RoHS package
US patent approved (NO 6799231)
accompany the sale of the product.
FAX: 886-3-579-9558
AX88780
Document No: AX88780/V1.4
Released Date: 5/18/2007
http://www.asix.com.tw

AX88780_07 Summary of contents

  • Page 1

    High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller Features ● High-performance non-PCI local bus 16/32-bit SRAM-like host interface Support big/little endian data bus type Large embedded SRAM for packet buffers 32K bytes for receive buffer 8K bytes for transmit buffer ...

  • Page 2

    Target Applications Multimedia applications Content distribution application Audio distribution system (Whole-house audio) Video-over IP solutions, IP PBX and video phone Video distribution system, multi-room PVR Cable, satellite, and IP set-top box Digital video recorder DVD recorder/player High definition TV Digital ...

  • Page 3

    Introduction.........................................................................................................................................................................7 1.1 General Description .......................................................................................................................................................7 1.2 AX88780 Block Diagram...............................................................................................................................................7 1.3 AX88780 Pinout Diagram..............................................................................................................................................8 2.0 Signal Description...............................................................................................................................................................9 2.1 Signal Type Definition ...................................................................................................................................................9 2.2 Host Interface.................................................................................................................................................................9 2.3 EEPROM Interface ......................................................................................................................................................10 2.4 Regulator Interface.......................................................................................................................................................11 2.5 10/100M PHY Interface ...............................................................................................................................................11 2.6 MII Interface ...

  • Page 4

    TXDES3--TX Descriptor3 Register ...........................................................................................................................23 4.12 RX_CFG--RX Configuration Register.......................................................................................................................23 4.13 RXCURT--RX Current Pointer Register ....................................................................................................................23 4.14 RXBOUND--RX Boundary Pointer Register ............................................................................................................24 4.15 MAC_CFG0--MAC Configuration0 Register............................................................................................................24 4.16 MAC_CFG1--MAC Configuration1 Register............................................................................................................24 4.17 MAC_CFG2--MAC Configuration2 Register............................................................................................................25 4.18 MAC_CFG3--MAC Configuration3 Register............................................................................................................25 4.19 TXPAUT--TX Pause ...

  • Page 5

    BMCR--Basic Mode Control Register.........................................................................................................................34 5.2 BMSR--Basic Mode Status Register............................................................................................................................35 5.3 PHYIDR0--PHY Identifier 0 Register .........................................................................................................................35 5.4 PHYIDR1--PHY Identifier 1 Register .........................................................................................................................36 5.5 ANAR--Auto-negotiation Advertisement Register ......................................................................................................36 5.6 ANLPAR--Auto-negotiation Link Partner Ability Register .........................................................................................36 5.7 ANER--Auto-negotiation Expansion Register .............................................................................................................37 6.0 ...

  • Page 6

    Figure 1: AX88780 block diagram ....................................................................................................................................... 7 Figure 2: AX88780 pin connection diagram......................................................................................................................... 8 Figure 3: 32-bit mode address mapping................................................................................................................................ 13 Figure 4: data swap block ..................................................................................................................................................... 14 Figure 5: 16-bit mode address mapping................................................................................................................................ 15 Figure 6: Transmit waveform specification ...

  • Page 7

    Introduction 1.1 General Description AX88780 supports full-duplex or half-duplex operation at 10/100 Mbps speed with auto-negotiation or manual setting. The AX88780 has two built-in synchronous SRAMs for buffering packet. The one is 32K bytes for receiving packets from Ethernet; ...

  • Page 8

    AX88780 Pinout Diagram The AX88780 is housed in the 128-pin LQFP package. 97 RSTPB 98 VCC25A 99 GNDA 100 VCC25A 101 GNDA 102 INTN 103 RST_N 104 HCLK 105 VCC33 106 GND 107 VCC25 108 HD31 109 HD30 110 ...

  • Page 9

    Signal Description 2.1 Signal Type Definition I3: Input, 3.3V with 5V tolerance I2: Input, 2.5V with 3.3V tolerance I25 Input, 2.5V only O3: Output, 3.3V O2: Output, 2.5V IO3: Input/Output, input 3.3V with 5V tolerance IO2 Input/Output, input 2.5V ...

  • Page 10

    HD19 IO3, 8mA 124 HD20 IO3, 8mA 122 HD21 IO3, 8mA 121 HD22 IO3, 8mA 120 HD23 IO3, 8mA 118 HD24 IO3, 8mA 116 HD25 IO3, 8mA 114 HD26 IO3, 8mA 113 HD27 IO3, 8mA 112 HD28 IO3, 8mA 111 ...

  • Page 11

    Regulator Interface Pin Name Type Pin No. VCC33R VCC3 37 GNDR GND 36 REG_EN I3 39 V25OUT O2 38 2.5 10/100M PHY Interface Table 4: 10/100M Twisted-pair signals group Pin Name Type Pin No. RXIN I 83 RXIP I ...

  • Page 12

    Miscellaneous Pin Name Type Pin No. LINKLED IO3, 55 12mA, PD SPDLED IO3, 54 12mA TEST0 I3 TEST1 I3 XTLN I25 90 XTLP O2 91 RSTPB I25 97 IBREF_WESD I25 88 ...

  • Page 13

    Functional Description 3.1 Host Interface AX88780 supports a very simple SRAM-like interface. There are only 3 control signals to operate the read or write. For write operation, host activates CSN and WEN to low with address and data bus. ...

  • Page 14

    Flow Control In full duplex mode, AX88780 supports the standard flow control mechanism defined in IEEE 802.3x standard. It enables the stopping of remote node transmissions via a PAUSE frame information interaction. When space of the packet buffer is ...

  • Page 15

    Mode AX88780 also supports 16-bit mode operation. AX88780 driver should request at least ( bytes space for TX, RX and register access. For example, the driver requests a 16K bytes space from system and then sets ...

  • Page 16

    EEPROM Format AX88780 will auto-load data from EEPROM device after hardware reset. If the EEPROM device is not attached, the loading operation will be discarded. The EEPROM mainly provides MAC address information and CIS information used ...

  • Page 17

    Register Description There are some registers located from offset 0xFC00 to 0xFCFF. All of the registers are 32-bit boundary alignment, but only low 16-bit are available (exception 0xFC54). For reserved bits, don’t set them in normal operation. Offset Name ...

  • Page 18

    CMD--Command Register Offset Address = 0xFC00 Field Name Type Default 31:16 - R/W All 0’s 15 RXVLAN R TXVLAN R/W 0 13:10 - R/W All 0’s 9 RXEN R TXEN R R/W ...

  • Page 19

    R DOGIM R RXFULIM R/W 0 4.3 ISR--Interrupt Status Register Offset Address = 0xFC08 Field Name Type Default 31 All 0’s 5 PHYIG R RPIG R FTPI R/W ...

  • Page 20

    TX_CFG--TX Configuration Register Offset Address = 0xFC10 Field Name Type 31 TXCRCAP R R/W 4 TXCHKSUM R/W 3 1:0 TXDS R 4.5 TX_CMD--TX Command Register Offset Address = 0xFC14 Field Name Type ...

  • Page 21

    TXD2O R TXD1O R TXD0O R/W 0 4.7 PHY_CTRL-- Internal PHY Control Register Offset Address = 0xFC1C Field Name Type 31: SPD_GPIO1 R/W 11 LNK_GPIO0 R/W 10 FUL_EECS R/W 9 PWDN R/W ...

  • Page 22

    TXDES0--TX Descriptor0 Register Offset Address = 0xFC20 Field Name Type Default 31: All 0’s 15 TXD0_EN R/W 0 14: 12:0 TXD0_LEN R/W All 0’s 4.9 TXDES1--TX Descriptor1 Register Offset Address = 0xFC24 Field Name ...

  • Page 23

    TXDES3--TX Descriptor3 Register Offset Address = 0xFC2C Field Name Type Default 31: All 0’s 15 TXD3_EN R/W 0 14: 12:0 TXD3_LEN R/W All 0’s 4.12 RX_CFG--RX Configuration Register Offset Address = 0xFC30h Field Name ...

  • Page 24

    RXBOUND--RX Boundary Pointer Register Offset Address = 0xFC38 Field Name Type Default 31: All 0’s 10:0 RXBUNPTR R/W 0x7FF 4.15 MAC_CFG0--MAC Configuration0 Register Offset Address = 0xFC40 Field Name Type Default 31: All 0’s 15 ...

  • Page 25

    R/W 0000 0 - R/W 0 4.17 MAC_CFG2--MAC Configuration2 Register Offset Address = 0xFC48 Field Name Type Default 15:8 - R/W 0x01 7:2 JamLT R/W 000000 1:0 - R/W 00 4.18 MAC_CFG3--MAC Configuration3 Register Offset Address = 0xFC4C ...

  • Page 26

    RXBTHD1--RX Buffer Threshold1 Register Offset Address= 0xFC5C Field Name Type Default 31: All 0’s 10:0 RXHIGHB R/W 0x600 4.22 RXFULTHD--RX Buffer Full Threshold Register Offset Address= 0xFC60 Field Name Type Default 31: All 0’s 10:0 ...

  • Page 27

    MACID0--MAC ID0 Register Offset Address = 0xFC70h Field Name Type Default 31: All 0’s 15:0 MID15_0 R/W 0x0000 4.25 MACID1--MAC ID1 Register Offset Address = 0xFC74 Field Name Type Default 31: All 0’s 15:0 MID31_16 ...

  • Page 28

    UNICAST R/W 1 MULTICAST R/W 0 RXANY R/W 4.29 MDIOCTRL--MDIO Control Register Offset Address = 0xFC84 Field Name Type Default 31: All 0’s 15 WTEN R RDEN R/W 0 12:8 PHYCRIDX R/W 00000 7:5 - ...

  • Page 29

    GPIO_CTRL--GPIO Control Register Offset Address = 0xFC8C Field Name Type Default 31: All 0’s 9 GPIO1S R GPIO0S R All 0’s 1 GPIO1DIR R GPIO0DIR R/W 1 Note: For ...

  • Page 30

    MDCLKPAT--MDC Clock Pattern Register Offset Address = 0xFCA0 Field Name Type Default 31: All 0’s 15:8 - R/W 0x80 7:0 MDCPAT R/W 0x40 4.35 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter Offset Address = 0xFCA4 Field Name Type Default ...

  • Page 31

    PROMCTRL--EEPROM Control Register Offset Address= 0xFCB4 Field Name Type Default 31: All 0’s 14:12 ROM_CMD R/W 000 11 ROM_WT R ROM_RD R ROM_RLD R 7:0 ROM_ADDR R/W 0x00 ...

  • Page 32

    HASHTAB1--Hash Table1 Register Offset Address = 0xFCC4 Field Name Type Default 31: All 0’s 15:0 HTAB1 R/W 0x0000 4.43 HASHTAB2--Hash Table2 Register Offset Address = 0xFCC8 Field Name Type Default 31: All 0’s 15:0 HTAB2 ...

  • Page 33

    SOFTRST – Software reset Register Offset Address = 0xFCEC Field Name Type Default 31 All 0’s 1 RST_PHY R RST_MAC R/W 1 Default = 0x0000_0003 Description Reserved Reset Internal PHY Driver set this bit to ...

  • Page 34

    PHY Register AX88780 is built a high performance 10/100M PHY for cost-effective. Driver can access these registers of PHY by in-directed mechanism. For write operation, software firstly sets data to MDIODP register, then sets index and write enable bit ...

  • Page 35

    COLTST R 5.2 BMSR--Basic Mode Status Register Index = 0x01 Field Name Type Default 15 100BCAP 100BFUL 100BHAF 10BFUL ...

  • Page 36

    PHYIDR1--PHY Identifier 1 Register Index = 0x03 Field Name Type Default 15:10 OUILSB R 000110 9:4 MANMODE R 000011 3:0 RECNUM R 0011 5.5 ANAR--Auto-negotiation Advertisement Register Index = 0x04 Field Name Type Default 15 NXTP ...

  • Page 37

    PNR100B PNR100BFUL PNR100BHAF PNR10BFUL PNR10BHAF R 0 4:0 PNRPROSEL R 00000 5.7 ANER--Auto-negotiation Expansion Register Index = 0x06 Field Name Type Default 15 All 0’s ...

  • Page 38

    Electrical Specification and Timings 6.1 DC Characteristics 6.1.1 Absolute Maximum Ratings Symbol T Storage Temperature STG VCC3 Power supply of 3.3V VCC2 Power supply of 2.5V V Input voltage of 3.3V IO with 5V tolerance I3 V Input voltage ...

  • Page 39

    DC Characteristics of 3.3V IO Pins Symbol Description VCC3 Power supply of 3.3V IO Vil Input low voltage Vih Input high voltage Vol Output low voltage Voh Output high voltage Rpu Input pull-up resistance Rpd Input pull-down resistance 6.1.6 ...

  • Page 40

    Power Consumption Device Only Measurement bases on 100MHz frequency of HCLK and turn on internal regulator at 25 Item Symbol Power-On with cable removed 1 VCC3 (IO) 1.6 2 VCC3R 103 Note: The current of VCC3R includes VCC2 core ...

  • Page 41

    Thermal Characteristics A. Junction to ambient thermal resistance, Symbol Min θ Junction to case thermal resistance, Symbol Min θ JC θ θ 1: Note , defined as below JA JC − θ θ J ...

  • Page 42

    Host Single Write Timing Tsetup HCLK CSN WEN HA[15:1] Tar HD[31:0] Tad Symbol Description Tsetup CSN, WEN to HCLK setup timing Tar HA exceed to WEN timing Tad HA exceed to WEN timing Tvalid_cycle A Valid write cycle timing ...

  • Page 43

    Host Burst Write Timing [15:1] A ddress alid data Symbol Description Twen Valid write cycle timing 6.2.5 Host Single Read Timing HCLK CSN/OEN HA[15:1] ...

  • Page 44

    Host Burst Read Timing HCLK CSN Tac Address (A1) OEN Tovd Invalid data Valid data (A1) Symbol Description Tac Valid address access timing Tovd OEN assert to valid data timing Tad Burst mode address to valid data Tdh Valid ...

  • Page 45

    MII Transmit Timing (100Mbps) TXCLK TXD[3:0] TXEN Tdelay Symbol Description Ttxclk TXCLK reference clock* Tdelay TXD[3:0], TXEN delay timing for TXCLK Tsetup TXD[3:0], TXEN setup time Thold TXD[3:0], TXEN hold time *Note: for 10Mbps, the typical value of Ttxclk ...

  • Page 46

    Serial EEPROM Timing ...

  • Page 47

    Package Information pin 1 b θ SYMBOL θ MILIMETER MIN. NOM 0.05 0.1 1.35 1.4 0.13 0.18 13.90 14.00 13.90 14.00 0.40 15.85 16.00 15.85 ...

  • Page 48

    Ordering Information AX88780 Product name L Package LQFP 48 ASIX ELECTRONICS CORPORATION AX88780 F F: Lead Free ...

  • Page 49

    Appendix A1. 16-bit mode address and data bus A1-1. 16-bit mode and separated address and data bus Note: The name of control signal for MCU is demonstrated only. A1-1-1. AX88780 is synchronous to host MCU ric ...

  • Page 50

    A1-2. 16-bit mode multiplexed address and data ...

  • Page 51

    Appendix A2. 32-bit mode address and data bus A2-1. Linear address mode and byte aligned (in synchronous mode ...

  • Page 52

    Appendix A3. Synchronous and asynchronous timing selection AX88780 can support synchronous or asynchronous access from host MCU. Below information provides some references to select clock frequency of host MCU and AX88780. A3-1. AX88780 is synchronous with host MCU. The timing ...

  • Page 53

    Appendix A4. Wake On LAN (WOL) without driver via Magic Packet A4-1. Wake On LAN (WOL) without driver AX88780 can support WOL without driver exists. In such situations, system must offer 3.3V voltage, reference clock and rest signal to AX88780. ...

  • Page 54

    Revision History Revision Date V1.0 2005/10/4 V1.1 2006/7/28 V1.2 2007/3/28 V1.3 2007/5/4 V1.4 2007/5/18 Comment First edition 1. Some typo errors corrected between Pin diagram and tables. 2. Host read/write timing revised in Section 5. 3. Some bits of registers ...

  • Page 55

    No.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. TEL: +886-3-5799500 FAX: +886-3-5799558 Email: support@asix.com.tw Web: http://www.asix.com.tw 55 AX88780 ASIX ELECTRONICS CORPORATION ...