AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 11

• Manufacturer Part Number: AX88780_07
• Description: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

2.4 Regulator Interface
2.5 10/100M PHY Interface
RXIN
RXIP
TXON
TXOP
2.6 MII Interface
TXEN
TXD[3:0]
TXCLK
RXCLK
RXD[3:0]
RXDV
COL
CRS
MDIO
MDC
PHYINTN I2
Pin Name
VCC33R
GNDR
REG_EN
V25OUT
Pin Name
Pin Name
O2, 12mA
O2, 12mA
I2
I2
I2
I2
I2
I2
IO2,
8mA,PU
O2, 8mA
Type
VCC3
GND
I3
O2
I
I
O
O
Type
Type
66
61,62,
63,65
69
71
77,76,75,
74
70
80
79
59
58
46
83
84
93
94
Pin No.
37
36
39
38
Pin No.
Pin No.
Table 4: 10/100M Twisted-pair signals group
Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes.
Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes
Transmit Enable:
Receive Data Valid:
Collision signal:
Station Management Data Clock:
An interrupt signal from PHY, active low.
Differential received input signal for both 10BASE-T and 100BSE-TX
(Note: please refer to Section 6.1.7 for detailed Transmission Characteristics)
Differential received input signal for both 10BASE-T and 100BSE-TX modes.
(Note: please refer to Section 6.1.6 for detailed Reception Characteristics)
TXEN is transition synchronously with respect to the rising edge of TXCLK. TXEN
indicates that the port is presenting nibbles on TXD [3:0] for transmission.
Transmit Data:
TXD[3:0] is transition synchronously with respect to the rising edge of TXCLK.
Transmit Clock:
TXCLK is a continuous clock from PHY. It provides the timing reference for the
transfer of the TXEN and TXD[3:0] signals from the MII port of PHY.
Receive Clock:
RXCLK is a continuous clock from PHY. It provides the timing reference for the
transfer of the RXDV, RXD[3:0] signals from MII port of PHY.
Receive Data:
RXD[3:0] is driven by the PHY synchronously with respect to RXCLK.
RXDV is driven by the PHY synchronously with respect to RXCLK. Asserted high
when valid data is present on RXD [3:0].
This signal is driven by PHY when collision is detected.
Carrier Sense:
Asynchronous signal CRS is asserted by the PHY when either the transmitted or
receive medium is non-idle.
Station Management Data Input /Output:
Serial data input/Output transfers from/to the PHY. The transfer protocol conforms to
the IEEE 802.3u MII specification.
The timing reference for MDIO. All data transfers on MDIO are synchronized to the
rising edge of this clock.
3.3V power to internal regulator
Ground pin for internal regulator
High to enable internal regulator. Low to disable internal regulator.
2.5V output from internal regulator, max 250mA, when REG_EN pin is high.
Table 5: MII Interface signals group
Table 3: Regulator signals group
11
Pin Description
Pin Description
Pin Description
ASIX ELECTRONICS CORPORATION
AX88780
modes.