AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 22

• Manufacturer Part Number: AX88780_07
• Description: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

4.8 TXDES0--TX Descriptor0 Register
Offset Address = 0xFC20
Field
31:16
15
14:13
12:0
4.9 TXDES1--TX Descriptor1 Register
Offset Address = 0xFC24
Field
31:16
15
14:13
12:0
4.10 TXDES2--TX Descriptor2 Register
Offset Address = 0xFC28
Field
31:16
15
14:13
12:0
Name
TXD0_EN
TXD0_LEN
Name
TXD1_EN
TXD1_LEN
Name
TXD2_EN
TXD2_LEN
-
-
-
-
-
-
Type
R
R/W
R
R/W
Type
R
R/W
R
R/W
Type
R
R/W
R
R/W
Default
All 0’s
0
00
All 0’s
Default
All 0’s
0
00
All 0’s
Default
All 0’s
0
00
All 0’s
Default = 0x0000_0000
Default = 0x0000_0000
Default = 0x0000_0000
Transmit TX descriptor 0
Reserved
Transmit TX descriptor 1
Reserved
Transmit TX descriptor 2
If this bit is enabled, MAC will begin to transmit data that are stored in TX
buffer. In former, data had been written to TX descriptor0. This bit will be
cleared by hardware when MAC finished the transmission.
1= enable
0= disable
TX packet length
Driver set this field to indicate AX88780 how many bytes will be
transmitted.
Reserved
If this bit is enabled, MAC will begin to transmit data that are stored in TX
buffer. In former, data had been written to TX descriptor1. This bit will be
cleared by hardware when MAC finished the transmission.
1= enable
0= disable
TX packet length (unit: byte)
Driver set this field to indicate AX88780 how many bytes will be
transmitted.
Reserved
If this bit is enabled, MAC will begin to transmit data that are stored in TX
buffer. In former, data had been written to TX descriptor2. This bit will be
cleared by hardware when MAC finished the transmission.
1= enable
0= disable
Reserved
TX packet length (unit: byte)
Driver set this field to indicate AX88780 how many bytes will be
transmitted.
Reserved
22
(unit: byte)
ASIX ELECTRONICS CORPORATION
Description
Description
Description
AX88780