AX88780_07 ASIX [ASIX Electronics Corporation], AX88780_07 Datasheet - Page 24

• Manufacturer Part Number: AX88780_07
• Description: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

4.14 RXBOUND--RX Boundary Pointer Register
Offset Address = 0xFC38
Field
31:11
10:0
4.15 MAC_CFG0--MAC Configuration0 Register
Offset Address = 0xFC40
Field
31:16
15
14
13
12
11
10:4
3:0
4.16 MAC_CFG1--MAC Configuration1 Register
Offset Address = 0xFC44
Field
31:15
14
13
12:7
6
5
Name
SPEED100
RXFLOW
IPGT
Name
PUSRULE
CRCCHK
DUPLEX
TXFLW_EN
Name
RXBUNPTR
-
-
-
-
-
-
-
-
Type
R
R/W
R/W
R/W
R/W
R/W
Type
R
R/W
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
All 0’s
1
1
All 0’s
0
0
Default
All 0’s
0x7FF
Default
All 0’s
1
0
0
0
0
0x15
0x7
Default = 0x0000_07FF
Default = 0x0000_8157
Default = 0x0000_6000
Reserved
Pause Frame Check Rule
When this bit is set, AX88780 accepts pause frame that DA can be any
value.
1 = don’t check DA field.
0 = check DA is equal to “01 80 C2 00 00 01”
Check CRC of received Packet.
When this bit is enabled, AX88780 will drop any CRC error packet.
1 = enable
0 = disable
Reserved, keep all bits in ‘0’ for normal operation.
Duplex Mode.
1 = Full-Duplex mode
0 = Half-Duplex mode
TX Flow Enable
When this bit is enabled, MAC will block the transmitted operation when it
captures pause frame from Ethernet. The re-transmission will be activated
Reserved
RX Line Boundary Pointer.
Point to the last line that has been read by driver. The unit of line is 16
bytes.
When driver finished reading packet from RX buffer, it must update this
field.
Reserved, this bit must set to 0 for normal operation
Reserved, this bit must set to 0 for normal operation.
Inter Packet Gap time: (IPG)
Reserved, keep the default value for normal operation.
Reserved
Line Speed Mode
When this bit is enabled, The MAC of AX88780 will operate in 100M
speed, otherwise it will operate in 10M speed. The line speed must
co-operate with setting of PHY.
1 = 100M
0 = 10M
RX Flow Control
If this bit and bit8 of RX_CFG are enabled, MAC will perform flow
control and send pause on/off frame when the available space of receive
buffer is less than the value of RXBTHD0.
1 = enable
0 = disable
Reserved, this bit must set to 0 for normal operation.
This field defines the back-to-back transmit packet gap for 10/100M only.
24
Description
ASIX ELECTRONICS CORPORATION
Description
Description
AX88780