AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet
AX88796BLI
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AX88796BLI Summary of contents
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... LQFP , RoHS package Operate over 0 to +70 °C or -40 to +85 °C temperature range US patent approved (NO 6799231) General processor AX88796B With 10/100 Mbps PHY FAX: 886-3-579-9558 AX88796BLF / AX88796BLI Document No.: AX88796B_17/08/18/07 Address AX88796B CSn With RDn / WRn Data Bus 10/100 Mbps PHY Interrupt First Released Date : 2006 / http://www ...
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... ELECTRICAL SPECIFICATION AND TIMINGS ............................................................................................62 8.0 PACKAGE INFORMATION .................................................................................................................................72 9.0 ORDERING INFORMATION ...............................................................................................................................73 APPENDIX A1: MCS51-LIKE (8-BIT)......................................................................................................................74 APPENDIX A2: ISA-LIKE (8/16-BIT) .......................................................................................................................75 APPENDIX A3: 186-LIKE (16-BIT)...........................................................................................................................76 APPENDIX A4: CO-WORK WITH 32-BIT PROCESSOR.....................................................................................77 APPENDIX A5: BIG-ENDIAN PROCESSOR OF DATA BYTE LANDS .............................................................79 APPENDIX B: DISABLE AX88796B VOLTAGE REGULATOR..........................................................................80 REVERSION HISTORY...............................................................................................................................................81 AX88796BLF / AX88796BLI CONTENTS 2 ASIX ELECTRONICS CORPORATION ...
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... MAC AGE OF ORE EGISTERS PHY MBEDDED EGISTERS SMI ANAGEMENT RAME MII ANAGEMENT RAMES AX88796BLF / AX88796BLI FIGURES .................................................................................................................................4 ...............................................................................................................................5 ...........................................................................................................16 .....................................................................................................................29 TABLES ........................................................................................................7 I ...........................................................................................7 NTERFACES PINS GROUP .........................................................................................................7 ............................................................................................................7 .................................................................................................................................8 .......................................................................................................................9 ......................................................................................................................28 M ....................................................................................................31 APPING M ....................................................................................................32 APPING M ....................................................................................................33 APPING M ....................................................................................................34 APPING ...
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... CPU interfaces including MCS-51 series, 80186 series, ISA bus and high-performance SRAM-like interface. The simple host interface provides a glue-less connection to most common microprocessors and microcontrollers. The AX88796B provides both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. 1.2 AX88796B Block Diagram: (Optional) AX88796BLF / AX88796BLI Fig - 1 AX88796B Block Diagram 4 ASIX ELECTRONICS CORPORATION ...
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... AEN,PSEN 51 CSn 52 RDn 53 WRn 54 IOIS16 55 TCLK 56 TEST_CK_EN 57 GND 58 VCCK 59 VCC18A 60 XTALIN 61 XTALOUT 62 GND18A 63 RSET_BG AX88796BLF / AX88796BLI AX88796B Fig - 2 AX88796B Pin Out Diagram 5 ASIX ELECTRONICS CORPORATION 32 SD10 31 SD11 30 SD12 29 SD13 28 SD14 27 SD15 26 GND 25 VCC3IO ...
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... IRQ O5/T5/8m CSn I5 RDn I5 WRn I5 IOIS16n T5/8m AEN or PSEN I5 AX88796BLF / AX88796BLI 8m 8mA driving strength S Schmitt trigger PU Internal Pull Up 75Kohm PD Internal Pull Down 75kohm P Power Pin A Analog System Address: Signals SA[4:0] are address bus input lines. Used to 50 select internal CSR’s. ...
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... EECS B5/4m/PD EECK B5/4m/PD EEDIO B5/4m/PU AX88796BLF / AX88796BLI 22 Wakeup Indicator: When programmed to do so, is asserted when the AX88696B detects a wake event and is requesting the system to wake up from the D1 sleep state. The polarity and buffer type of this signal is programmable by BTCR (offset 15h) Tab - 1 Local CPU bus interface signals group ...
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... VCC3IO P 25, 44 VCCK P 24, 43, 59 AX88796BLF / AX88796BLI 61 Crystal/Oscillator Input: A 25Mhz crystal, +/- 50 PPM can be connected across XTALIN and XTALOUT. CMOS Local Clock: A 25Mhz clock, +/- 50 PPM, 40%-60% duty cycle. Note that the pin does not support 3. voltage supply. 62 Crystal/Oscillator Output: A 25Mhz crystal, +/- 50 PPM can be connected across XTALIN and XTALOUT ...
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... PHY_CONFIG [7:6] [5] [4] [3] [2] [1:0] 1h [15:0] 00h 0h [15:0] 5Ah AX88796BLF / AX88796BLI D[7:0] th 98h MAC address 6 th 54h MAC address 4 nd 10h MAC address 2 Always zero Configure internal PHY in different ways, such as 10BASE_T half-duplex mode. If EEPROM auto loader not found 5AA5h pattern in first word then internal PHY will be not been manual configuration ...
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... SRAM Address 40EH 0406H ~ 040DH 0404H 0402H 0400H AX88796BLF / AX88796BLI Function AX88796B Command Status Register Tab - 7 CSR Address Mapping Function Load from EEPROM Reserved Load from EEPROM Reserved NE2000 compatible mode SRAM Buffer Reserved ...
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... Address of last BYTE in packet buffer SRAM is Page 0x7F, offset 0xff Page 0x7F (7F00h) Page 0x80 (8000h) AX88796BLF / AX88796BLI 0h ~ 1Fh, Auto load MAC address from external EEPROM 20h ~ 03FFh, Reserved 0400h ~ 040Fh, Auto load MAC address from external EEPROM 0410h ~ 3FFFh, Reserved ...
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... MAR1 FB15 FB14 MAR2 FB23 FB22 MAR3 FB31 FB30 MAR4 FB39 FB38 MAR5 FB47 FB46 MAR6 FB55 FB54 MAR7 FB63 FB62 AX88796BLF / AX88796BLI DA5 DA4 DA3 DA13 DA12 DA11 DA21 DA20 DA19 DA29 DA28 DA27 DA37 DA36 DA35 DA45 DA44 ...
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... The maximum length of the good packet is thus change from 1518 bytes to 1522 bytes. 7 Bytes 1 Byte 6 Bytes Destination Layer 2 Preamble SFD Address Frame (64-1518 Bytes) VLAN (64-1522 Bytes) AX88796BLF / AX88796BLI Selected bit 0 = reject, 1= accept 802.1Q VLAN tagging 6 Bytes Source 8100 TCI ...
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... The meaning of AB, AM and PRO signals, please refer to “Receive Configuration Register” RCR (offset 0Ch) The meaning of VLANE signal, Please refer to “MAC Configure Register” MCR (offset 1Bh) Aggregate Address Filter function will be: Bro AB /Bro /Mul PRO /Bro Mul AM Phy VID VLANE AX88796BLF / AX88796BLI AGG 14 ASIX ELECTRONICS CORPORATION ...
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... DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address. Page Start Buffer #1 Buffer #2 Buffer #3 … … … … Buffer #n Page Stop Physical Memory Map AX88796BLF / AX88796BLI 4000h n-2 n-1 8000h Logic Receive Buffer Ring Fig - 4 Receive Buffer Ring 15 ASIX ELECTRONICS CORPORATION 4 … 3 ...
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... When linking buffers, buffer management will never cross this pointer, effectively avoiding any overwrites. If the buffer address does not match either the Boundary Pointer or Page Stop Address, the link to the next buffer is performed. AX88796BLF / AX88796BLI 4000h … ...
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... This operation will not be performed if the AX88796B is programmed to accept either runt packets or packets with CRC or Frame Alignment errors. The received CRC is always stored in buffer memory after the last byte of received data for the packet. AX88796BLF / AX88796BLI Description D[15:8]: Next Page Pointer ...
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... TPSR and TBCR1, 0 from TX Command Queue then transmit this packet following CSMA/CD protocol recommended to enable this function to enhance TX performance. AX88796BLF / AX88796BLI Transmit buffer Receive buffer Transmit buffer Receive buffer TX Command Queue Push In TPSR TBCR 1, 0 AX88796B will report Current of Transmit End Page CTEPR (offset 1Ch) when every packet transmits completed ...
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... The COL bit will be set in the TSR and the NCR (Number of Collisions Register) will be incremented retransmissions each result in a collision the transmission will be aborted and the ABT bit in the TSR will be set. AX88796BLF / AX88796BLI 6 Bytes 6 Bytes ...
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... This format is used with ISA or MCS-51 Mode. Note: All examples above will result in a transmission of a packet in order of DA0 (Destination Address 0), DA1, DA2, DA3 and byte. Bits within each byte will be transmitted least significant bit first. AX88796BLF / AX88796BLI D8 D7 D[7:0] Destination Address 0 ...
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... Note the size of the Receive Buffer Ring is reduced by one 256-byte buffer; this will not, however, impede the operation of the AX88796B. The advantage of this scheme is that it easily differentiates between buffer full and buffer empty full when BNRY = CPR empty when BNRY = CPR-1. AX88796BLF / AX88796BLI 21 ASIX ELECTRONICS CORPORATION ...
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... Data 1 … WTS = 1 in Data Configuration Register. This format is used with ISA or 80186 Mode. D7 WTS = 0 in Data Configuration Register. This format is used with ISA or MCS-51 Mode. AX88796BLF / AX88796BLI D8 D7 Receive Status Receive Byte Count 0 Destination Address 0 Destination Address 2 Destination Address 4 Source Address 0 ...
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... Issue the TXP command to the AX88796B. This can be accomplished by writing 26h to the Command Register. 7. Read data current receive buffer by Remote DMA read operation. 8. Compare the received data with original transmit data and check equal. 9. Repeat step 5 to step 8 for more packets test. AX88796BLF / AX88796BLI 23 ASIX ELECTRONICS CORPORATION ...
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... Wakeup Frame 1 CRC Wakeup Frame 3 CRC Offset 3 Last Byte 3 Reserved Wake-Up frame Byte Mask Register Structure AX88796BLF / AX88796BLI [15:8] [23:16 Byte Mask 0 ...
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... CRC (4 byte) AX88796BLF / AX88796BLI page3 ...
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... A XOFF transmitting when the total of free page count equal to or greater then (“high water free-page-count” pages). STOP TX RX AX88796B PAUSE frame TX Flow Control AX88796BLF / AX88796BLI Length/Type MAC Control Source (2-bytes) Opcode MAC = 802.3 MAC ...
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... GPT, and continues counting. The GPT interrupt has no status indicate in Interrupt Status Register (CR page0 offset 07h). The interrupt event will keep active until host driver read Interrupt Status Register (CR page0 offset 07h) then clear GPT interrupt event. AX88796BLF / AX88796BLI DESCRIPTION SD[15:8] ...
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... Up Register” (Offset 1Fh) return the AX88796B to the D0 state. Power is reduced to various modules by disabling the clocks as outlined in table as below. AX88796B BLOCK Internal clock MAC and Host MAC power management PHY AX88796BLF / AX88796BLI 93C46 EECS EECS EECK EECK EEDI EEDIO EEDO Fig - 7 EEPROM connections D0 ...
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... This RDMA-RDY will be cleared when host write “Remote Byte Count 0” RBCR0 (CR page0 Offset 0Ah) or “Remote Byte Count 1” RBCR1 (CR page0 Offset 0Bh). The byte counter will down counting when every data port (DP) access. This RDMA-RDY will be set when byte counter count to zero. AX88796BLF / AX88796BLI 60ms Fig - 8 PME and IRQ signal generation ...
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... Device Status Register (DSR) / Back-pressure Jam Limit Count (BJLC) 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH AX88796BLF / AX88796BLI Page1 Command Register (CR) Data Port (DP) Inter-frame Gap Segment 1 (IFGS1) Inter-frame Gap Segment 2 (IFGS2) MII/EEPROM Access Buffer Type Configure Register (BTCR) Inter-frame Gap (IFG) ...
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... Current TX End Page Register (CTEPR) 1DH Reserved 1EH Reserved 1FH Software Reset Tab - 13 Page 0 of MAC Core Registers Mapping AX88796BLF / AX88796BLI Write Command Register (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY) Transmit Page Start Address (TPSR) Transmit Byte Count Register 0 (TBCR0) ...
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... Multicast Address Register 5 (MAR5) 0EH Multicast Address Register 6 (MAR6) 0FH Multicast Address Register 7 (MAR7) Tab - 14 Page 1 of MAC Core Registers Mapping AX88796BLF / AX88796BLI Write Physical Address Register 0 (PAR0) Physical Address Register 1 (PAR1) Physical Address Register 2 (PAR2) Physical Address Register 3 (PAR3) ...
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... Chip version (00h) 0CH Receive Configuration Register (RCR) 0DH Transmit Configuration Register (TCR) Reserved 0EH Data Configuration Register (DCR) 0FH Interrupt Mask Register (IMR) Tab - 15 Page 2 of MAC Core Registers Mapping AX88796BLF / AX88796BLI Write Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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... WFLB 09H WFCMD 0AH WUCSR 0BH PMR 0CH Reserved 0DH MISC 0EH GPT0 0FH GPT1 Tab - 16 Page 3 of MAC Core Registers Mapping AX88796BLF / AX88796BLI Write WFBM0 WFBM1 WFBM2 WFBM3 WF10CRC WF32CRC WFOFST WFLB WFCMD WUCSR PMR REER MISC GPT0 GPT1 ...
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... This bit always read high when Host set once. It only clear by hardware or software reset. 0 STOP STOP: Stop AX88796B This bit is used to stop the AX88796B operation. It will be reset to default value when set PMR sleep state. AX88796BLF / AX88796BLI 0 page 0 (default) 1 page 1 0 ...
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... Indicates that the transmission collided at least once with another station on the network Reserved 0 PTX Packet Transmitted Indicates transmission without error. 5.1.7 Transmit Byte Count Register (TBCR0) Page0 Offset 05H (Write) Field Name Description 7:0 TBCR0 Transmit Byte Count Register. The bit assignment is shown below AX88796BLF / AX88796BLI 36 ASIX ELECTRONICS CORPORATION ...
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... Write this bit to high then reset it. 1 PTX Packet Transmitted Indicates packet transmitted with no error Write this bit to high then reset it. 0 PRX Packet Received Indicates packet received with no error. Write this bit to high then reset it. AX88796BLF / AX88796BLI 37 ASIX ELECTRONICS CORPORATION ...
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... Current Remote DMA Address (CRDA1) Page0 Offset 09H (Read) Field Name Description (Default = 00h) 7:0 CRDA1 The Current Remote DMA Registers contain the current address of the Remote DMA. The bit assignment is shown below: AX88796BLF / AX88796BLI 38 ASIX ELECTRONICS CORPORATION ...
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... Receive Status Register (RSR) Page0 Offset 0CH (Read) Field Name Description (Default = 00h Reserved 6 DIS Receiver Disabled 5 PHY Multicast Address Received. 4 MPA Missed Packet 3 - Always Zero 2 FAE Frame alignment error CRC error. 0 PRX Packet Received Intact AX88796BLF / AX88796BLI 39 ASIX ELECTRONICS CORPORATION ...
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... Name Description (Default = 00h) 7:0 CNTR1 This counter is incremented every time a packet is received with a CRC error. The packet must first be recognized by the address recognition logic. The counter is cleared after the processor reads it. AX88796BLF / AX88796BLI 0 Normal operation (Default) 1 Internal AX88796B loop-back 0 PHY loop-back ...
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... Page0 Offset 0FH (Read) Field Name Description (Default = 00h) 7:0 CNTR2 This counter is incremented if a packet cannot be received due to lack of buffer resources. In monitor mode, this counter will count the number of packets that pass the address recognition logic. AX88796BLF / AX88796BLI 41 ASIX ELECTRONICS CORPORATION ...
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... The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in PAR0 ~ PAR5 to the bit sequence of the received packet. AX88796BLF / AX88796BLI 42 ASIX ELECTRONICS CORPORATION ...
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... Multicast Address Register 5 5.1.39 Multicast Address Register 6 (MAR6) Page1 Offset 0EH (Read/Write) Field Name Description (Default = 00h) 7:0 MAR6 Multicast Address Register 6 5.1.40 Multicast Address Register 7 (MAR7) Page1 Offset 0FH (Read/Write) Field Name Description (Default = 00h) 7:0 MAR7 Multicast Address Register 7 AX88796BLF / AX88796BLI 43 ASIX ELECTRONICS CORPORATION ...
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... Page2 Offset 0EH (Read) Field Name Description (Default = 00h) 7:0 DCR Reference Page0 Offset 0EH for bits deifications. 5.1.45 Interrupt Mask Register (IMR) Page2 Offset 0FH (Read) Field Name Description (Default = 00h) 7:0 IMR Reference Page0 Offset 0FH for bits deifications. AX88796BLF / AX88796BLI 44 ASIX ELECTRONICS CORPORATION ...
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... WF2_0CRC Byte mask CRC for wake-up frame filter 2. Host continue write 4 times to completed 32-bits of Byte Mask 3 CRC and Byte Mask 2 CRC. CRC-16 Polynomials = X^16 + X^ 15:8 WF2_1CRC Byte mask CRC for wake-up frame filter 2. 23:16 WF3_0CRC Byte mask CRC for wake-up frame filter 3. 31:24 WF3_1CRC Byte mask CRC for wake-up frame filter 3. AX88796BLF / AX88796BLI 45 ASIX ELECTRONICS CORPORATION ...
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... MPR Magic Packet Received event flag. This bit will be clear when Host write PMR or set this bit Reserved 2 LSCWE Link status change wakeup enable 0: disable (Default) 1: enable 1 WUEN Wake-up frame enable 0: disable (Default) 1: enable AX88796BLF / AX88796BLI 46 ASIX ELECTRONICS CORPORATION ...
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... Remote DMA write transmit buffer as a Ring from page 40h to PSTART –1. 5.1.59 General Purpose Timer0 Register (GPT0) Page3 Offset 0EH (Write/Read) Field Name Description (Default = FFh) 7:0 - General Purpose Timer [7:0] 5.1.60 General Purpose Timer1 Register (GPT1) Page3 Offset 0FH (Write/Read) Field Name Description (Default = FFh) 7:0 - General Purpose Timer [15:8] AX88796BLF / AX88796BLI 47 ASIX ELECTRONICS CORPORATION ...
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... Signal Direction: for both of SMI (MDIO) and EEPROM (EEDIO) 0: output direction, MDIO and EEDIO as push-pull drive out 1: input direction, MDIO and EEDIO as Z state for source from external signals 0 MDC MDC MII Clock. It connect to internal PHY of MDC AX88796BLF / AX88796BLI 48 ASIX ELECTRONICS CORPORATION ...
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... System interrupt event PME_IRQ_EN (offset 15h) MPEN (CR page3 offset 0Ah) Magic Packet Detect event WUEN (CR page3 offset 0Ah) Wakeup Frame Detect event PME_IND (offset 15h) PME_POL (offset 15h) PME_TYPE (offset 15h) AX88796BLF / AX88796BLI logic ENB logic 60ms ENB 49 ASIX ELECTRONICS CORPORATION IREQ ...
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... MAX Frame size [7:0], default {MFSR1, MFSR0} = 1536 bytes 5.1.70 MAX Frame Size Register (MFSR1) Offset 19H (Read/Write) Field Name Description (Default = 06h) 7:3 - Reserved 2:0 MFSR1 MAX Frame size [10:8] AX88796BLF / AX88796BLI IFG 15h – n 15h (default) 15h + n 50 ASIX ELECTRONICS CORPORATION Bit-time of Frame gap 96 – (4* (4*n) ...
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... Others as normal. 1 SPMAC Super MAC. 0: always write low (Default) 1: for MAC test only. Back-off only slot-time 0 ZEROBF Zero Back Off Time. 0: always write low (Default) 1: for MAC test only. Back Off Time always zeros. AX88796BLF / AX88796BLI 51 ASIX ELECTRONICS CORPORATION ...
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... Host Wake Up Register (HWUR) Offset 1FH (Write) Field Name Description 7:1 - Reserved 0 HWAKE Host write one to wake up AX88796B from D2 power saving. It will be auto clear when (SC) wake up. 5.1.78 Software Reset Offset 1FH (Read) Field Name Description 7:0 - Don’t care this read value. AX88796BLF / AX88796BLI 52 ASIX ELECTRONICS CORPORATION ...
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... Bit set to logic one 0: Bit set to logic zero X: No set value Access type RO: Read only RW: Read or write Attribute SC: Self-clearing PS: Value is permanently set LL: Latch low LH: Latch high AX88796BLF / AX88796BLI Default value 3100H 7809H 003BH 1841H 01E1H 0000H 0000H Tab - 17 The Embedded PHY Registers 53 ...
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... R/W 0.9 (REDONWAY Restart Autonegotiation. 0.8 (FULL_DUP 0.7 (COLTST 0.6:0 (RESERVED AX88796BLF / AX88796BLI Description (Default = 3100h Normal operation 1 = Loop-back enabled 0 = Normal operation 1 = 100Mbits 10Mbits Auto negotiation enabled. Bits 8 and 13 of this register are ignored when this bit is set Auto negotiation disabled. Bits 8 and 13 of this register determine the link speed and mode ...
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... Link Status. 1.1 (JABBER Jabber Detect. 1.0 (EXT_ABLE Extended Capability. AX88796BLF / AX88796BLI Description (Default = 7809h AX88796B is not able to perform in 100BASE-T4 mode 1 = AX88796B is able to perform in 100BASE-TX full duplex mode 1 = AX88796B is able to perform in 100BASE-TX half duplex mode 1 = AX88796B is able to perform in 10BASE-T full duplex mode 1 = AX88796B is able to perform in 10BASE-T half duplex mode Reserved ...
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... R/W 4.5 (10BASET) R/W 4.4:0 (SELECT) [0 0001], RW AX88796BLF / AX88796BLI Description (Default = 003Bh) Organizationally Unique Identifier. The third through the twenty-fourth bit of the OUI assigned to the PHY manufacturer by the IEEE are to be placed in bits. 2.15:0 and 3.15:10. Description (Default = 1841h) Organizationally Unique Identifier. The remaining 6 bits of the OUI. ...
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... RO 5.6 (LP_ 10_FD 5.5 (LP_ 10_HD 5.4:0 (LP_SELECT) [0 0000], RO AX88796BLF / AX88796BLI Description (Default = 0000h) Link Partner Next Page Link partner is next page able 0 = Link partner is not next page able Link Partner Acknowledge Link partner reception of data word acknowledged 0 = Not acknowledged Remote Fault. ...
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... Next Page Able. (NEXT_PAGE_ABLE) 6.1 (PAGE_REC Page Received. 6 (LP_NWAY_ABLE) AX88796BLF / AX88796BLI Description (Default = 0000h) Reserved. Write as 0, read as “don’t care” Fault detected via the parallel detection function fault detected Link Partner Next Page Able Link partner is next page able ...
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... DP and WTS=1) 80186 CPU bus Write function Function Mode CSn A0 Standby Mode H X Byte Access L L (For all of CSR L H except DP) Word Access L L (Only for DP and WTS=1) AX88796BLF / AX88796BLI A0 RDn WRn RDn WRn X X ...
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... PSEN Standby Mode Byte Access 8051 bus Write function Function Mode CSn PSEN Standby Mode Byte Access AX88796BLF / AX88796BLI SA0 RDn WRn SA0 RDn WRn ...
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... IDLE Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be disabled and the PHY’s pull-up resistor will pull the MDIO line to logic 1. Tab - 19 MII Management Frames- field Description AX88796BLF / AX88796BLI (Internal PHY) MDC MDIO-OUT Fig - 9 SMI connections ...
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... Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Input pull-up resistance Input pull-down resistance Input Leakage with pull-up resistance (Vin=0) Current with pull-down resistance(Vin=VCC3I) Tri-state Output Leakage Current AX88796BLF / AX88796BLI Rating -0.3 to 2.16 -0.3 to 4.0 -0.3 to 5.8 -65 to 150 20 20 Symbol Min ...
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... C14 C15 + 0.1uF 10uF 10V 22uF/16V 0.1uF 0.1uF 0.1uF VCC18 VCC18 L2 C18 C19 C20 C26 F.B. C28 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10V AX88796BLF / AX88796BLI Operating at Operating at PHY power 10BASE-T 100BASE 118 165 390 U1 SA1 49 32 SA1 SD10 ...
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... Reset Timing RSTn Configuration Signals Output Drive Symbol Trst Reset pulse width Is Configuration input setup to RSTn rising Ih Configuration input hold after RSTn rising Oen Output driver after RSTn rising AX88796BLF / AX88796BLI Trst Trst Is Description 64 Ih Oen Min Typ. Max Units 200 ...
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... RDn HI REQUIRE TIME Tdon DATA BUFFER TURN ON TIME Tdoff DATA BUFFER TURN OFF TIME Tcycle READ CYCLE TIME Base on SD bus output load 25pF Base on SD bus output load 50pF AX88796BLF / AX88796BLI Tasu Trdl Trdl Tdv Tdon Tonis16 Description Min ...
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... IOIS16n VALID FROM SA[5:0], CSn AND AEN Toffis16 IOIS16n DISABLE FROM SA[5:0], CSn AND AEN Tds DATA STABLE TIME Tdh DATA HOLD TIME Twrl WRn WIDTH TIME Twrh WRn HI REQUIRE TIME Tcycle WRITE CYCLE TIME AX88796BLF / AX88796BLI Tcycle Tcycle Tasu Twrl Twrl Tds Tonis16 Description Min ...
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... Tdon DATA BUFFER TURN ON TIME Tdoff DATA BUFFER TURN OFF TIME Tcycle READ CYCLE TIME Base on SD bus output load 25pF Base on SD bus output load 50pF AX88796BLF / AX88796BLI Tas u Trdl Trdl Tdv Tdon Description Min ASIX ELECTRONICS CORPORATION ...
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... ADDRESS SETUP TIME Tah ADDRESS HOLD TIME Tds DATA STABLE TIME Tdh DATA HOLD TIME Twrl WRn WIDTH TIME Twrh WRn HI REQUIRE TIME Tcycle WRITE CYCLE TIME AX88796BLF / AX88796BLI Tas Tds Description Min ASIX ELECTRONICS CORPORATION Tah ...
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... Tdon DATA BUFFER TURN ON TIME Tdoff DATA BUFFER TURN OFF TIME Tcycle READ CYCLE TIME Base on SD bus output load 25pF Base on SD bus output load 50pF AX88796BLF / AX88796BLI Tasu Trdl Trdl Tdv Tdon Description Min ASIX ELECTRONICS CORPORATION ...
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... ADDRESS SETUP TIME Tah ADDRESS HOLD TIME Tds DATA STABLE TIME Tdh DATA HOLD TIME Twrl WRn WIDTH TIME Twrh WRn HI REQUIRE TIME Tcycle WRITE CYCLE TIME AX88796BLF / AX88796BLI Tasu Tds Description Min ASIX ELECTRONICS CORPORATION Tah ...
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... RDn HI REQUIRE TIME Tacyc READ CYCLE TIME Tdon DATA BUFFER TURN ON Tdoff DATA BUFFER TURN OFF Base on SD bus output load 25pF Base on SD bus output load 50pF AX88796BLF / AX88796BLI Tacy c Tacy c Tadv Tadv Description Min ASIX ELECTRONICS CORPORATION Tacyc Tacyc ...
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... Package Information pin 1 b θ Symbol θ AX88796BLF / AX88796BLI Dimension (mm) MIN. TYP 0.05 1.35 1.40 0.13 0.18 7.00 7.00 0.40 9.00 9.00 0.45 0.60 1.00 0° 3.5° 72 ASIX ELECTRONICS CORPORATION MAX 0.15 1.45 1.60 0.23 0.75 7° ...
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... Ordering Information Model NO 64 PIN, LQFP Package, Commercial grade 0°C to +70 °C (Green, AX88796BLF Lead-Free) 64 PIN, LQFP Package, Industrial grade -40°C to +85 °C (Green, AX88796BLI Lead-Free) AX88796BLF / AX88796BLI Description 73 ASIX ELECTRONICS CORPORATION ...
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... Offset 1A 1B Offset 1B Offset 1B 1C Offset 1D Offset 1C 1D Offset 1D Offset effect Offset 1E 1F (Reset) *1 (Reset) *1 Read offset 1Fh register will reset AX88796B AX88796BLF / AX88796BLI AX88796B SA0 SA1 SD[15:8] SA2 SA3 SA4 SA5/FIFO_SEL AEN/PSEN SD[7:0] RDn WRn IRQ AX88796B Host Addr CSR Offset A[5:0] ...
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... Offset 1A 1B Offset 1B Offset 1B 1C Offset 1D Offset 1C 1D Offset 1D Offset effect Offset 1E 1F (Reset) *1 (Reset) *1 Read offset 1Fh register will reset AX88796B AX88796BLF / AX88796BLI AX88796B SA0 SA1 SA2 SA3 SA4 SA5/FIFO_SEL AEN/PSEN SD[15:0] RDn WRn IRQ AX88796B Host Addr CSR Offset A[5:0] 0 ...
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... Offset 1A 1B Offset 1B Offset 1A 1C Offset 1D Offset 1C 1D Offset 1D Offset effect Offset 1E 1F (Reset) *1 (Reset) *1 Read offset 1Fh register will reset AX88796B AX88796BLF / AX88796BLI AX88796B SA0 SA1 SA2 SA3 SA4 SA5/FIFO_SEL AEN/PSEN SD[15:0] RDn WRn IRQ AX88796B Host Addr CSR Offset A[5:0] 0 ...
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... Offset 13 Offset 12 26 Offset 13 Offset 13 28 Offset 15 Offset 14 2A Offset 15 Offset 15 2C Offset 17 Offset 16 2E Offset 17 Offset 17 AX88796BLF / AX88796BLI AX88796B A5/FIFO_SEL CSn RDn WRn IRQ AEN/PSEN AX88796B Host Addr SD[15:8] CSR Offset A[11: effect effect ...
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... Offset 1B 38 Offset 1D Offset 1C 3A Offset 1D Offset effect Offset 1E 3E (Reset) *1 (Reset) 40 ~7FF No used No used 800 ~ FFF (DP) (DP) *1 Read offset 1Fh register will reset AX88796B AX88796BLF / AX88796BLI used 40 ~7FF 10 (DP) 800 ~ FFF ...
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... An example, AX88796B co-work with big-endian processor like Renesas H8/SH2 MCU, etc.. (To support big-endian processors, the hardware designer must explicitly swap the connection of data byte lanes.) ADDR D[7:0] D[15:8] CSn RDn WRn INT Big-endian Processor AX88796BLF / AX88796BLI AX88796B ADDR D[7:0] D[15:8] CSn RDn WRn IRQ 79 ASIX ELECTRONICS CORPORATION ...
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... Logic “low” Note: If user connects the VCC3R3 to 3.3V VCC and wants to disable the internal voltage regulator of AX88796B, the REGSTB bit of PMR register should be set set the regulator in standby mode to reduce the leakage current. AX88796BLF / AX88796BLI AX88796B Keep NC without loading V18F REGSTB Supply Analog 1 ...
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... V1.5 2007/3/19 V1.6 2007/4/27 V1.7 2007/8/18 AX88796BLF / AX88796BLI Comment Initial Release. 1. Correct some typo errors. 2. Change page3 offset 0Dh register name from P30D to MISC. 3. Change the name of bit 5 of MCR register from TQCE to BBTC. 4. Define a short name “TXCQF” for bit 7 of CTEPR register. ...
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... No.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. TEL: +886-3-5799500 FAX: +886-3-5799558 Email: support@asix.com.tw Web: http://www.asix.com.tw 82 AX88796BLF / AX88796BLI ASIX ELECTRONICS CORPORATION ...