AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 15

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

4.2 Buffer Management Operation
4.2.1 Packet Reception
Page Start
Page Stop
There are four buffer memory access types used in AX88796B.
The type 1 and 2 operations act as Local DMA. Type 1 does Local DMA write operation and type 2 does Local
DMA read operation. The type 3 and 4 operations act as Remote DMA. Type 3 does Remote DMA write operation
and type 4 does Remote DMA read operation.
The Local DMA receives channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256
byte (128 word) buffers for storage of received packets. The location of the Receive Buffer Ring is programmed in
two registers, a Page Start and a Page Stop Register. Ethernet packets consist of minimum packet size (64 bytes) to
maximum packet size (1522 bytes), the 256 byte buffer length provides a good compromise between short packets
and longer packets to most efficiently use memory. In addition these buffers provide memory resources for storage
of back-to-back packets in loaded networks. Buffer Management Logic in the AX88796B controls the assignment
of buffers for storing packets. The Buffer Management Logic provides three basic functions: linking receive buffers
for long packets, recovery of buffers when a packet is rejected, and recalculation of buffer pages that have been read
by the host.
At initialization, a portion of the 16k byte (or 8k word) address space is reserved for the receiver buffer ring. Two
eight bit registers, the Page Start Address Register (PSTART) and the Page Stop Address Register (PSTOP) define
the physical boundaries of where the buffers reside. The AX88796B treats the list of buffers as a logical ring;
whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address.
1. Packet Reception (Write data to memory from MAC)
2. Packet Transmission (Read data from memory to MAC)
3. Filling Packets to Transmit Buffer (Host fill data to memory)
4. Removing Packets from the Receive Buffer Ring (Host read data from memory)
Physical Memory Map
Buffer #1
Buffer #2
Buffer #3
Buffer #n
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Fig - 4 Receive Buffer Ring
4000h
8000h
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AX88796BLF / AX88796BLI
n-2
n-1
Logic Receive Buffer Ring
ASIX ELECTRONICS CORPORATION
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n
4
1
3
2