AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 18

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

4.2.2 Packet Transmission
The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer during
transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0, 1).
When the AX88796B receives a command to transmit the packet pointed to by these registers, buffer memory data
will be moved into the FIFO as required during transmission. The AX88796B Controller will generate and append
the preamble, synch and CRC fields. AX88796B supports options of transmit queue function to enhance transmit
performance.
Original NE2000 Of Transmit Buffer
Options Of Transmit Buffer As A Ring
Options Back-To-Back Transmission (TX Command Queue)
AX88796B
write default operation is
continue to write next address
even over transmit buffer
area. Host can do whole
memory read / write testing.
And host must handle the
transmit data do not overwrite
receive buffer area when
performing fill transmit data
to transmit buffer.
When active Transmit Buffer
Ring Enable (CR page3 of
offset
remote DMA write operation
will role over from last
transmit page to first transmit
page. Host no need reassign
RSAR0, RSAR1 again to fill
transmit data for first page.
When active TX Queue Enable
(offset 1Bh), Host can continue
Writing TXP (bit 2 of CR
register) to push TPSR and
TBCR1, 0 into AX88796B TX
command queue as long as
Transmit buffer has enough
vacancy and
1Ch) bit7 is ‘0’(Not full). After
current
completely, MAC TX will pop
out next TPSR and TBCR1, 0
from TX Command Queue
then
following CSMA/CD protocol.
It is recommended to enable
this function to enhance TX
performance.
transmit
0Dh).
packet
remote
CTEPR (offset
this
AX88796B
transmitted
DMA
packet
Push In
Transmit buffer
Receive buffer
Transmit buffer
Receive buffer
AX88796B will report Current of Transmit End Page
CTEPR (offset 1Ch) when every packet transmits
completed.
Host can understand AX88796B current of transmitting
buffer point by reading CTEPR.
TPSR
TBCR
1, 0
TX Command Queue
18
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION
TX Page Start Address (0x40)
TX Page Start Address (0x40)
Rx Page Start Register,
PSTART (CR page0, offset
01h)
Rx Page Start Register,
PSTART (CR page0, offset
01h)
Pop Out
MAC TX
function block