AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 26

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

4.4 Flow Control
4.4.1 Full-Duplex Flow Control
The AX88796B supports Full-duplex flow control using the pause control frame. It also supports half-duplex flow
control using collision base of back-pressure method.
The format of a PAUSE frame is illustrated below. It conforms to the standard Ethernet frame format but includes a
unique type field and other parameters as follows:
The destination address of the frame may be set to either the unique DA of the station to be paused, or to the globally
assigned multicast address 01-80-C2-00-00-01 (hex). The IEEE 802.3 standard for use in MAC control PAUSE
frames has reserved this multicast address. The "Type" field of the PAUSE frame is set to 88-08 (hex) to indicate the
frame is a MAC Control frame.
The MAC Control opcode field is set to 00-01 (hex) to indicate the type of MAC Control frame being used is a
PAUSE frame. The PAUSE frame is the only type of MAC Control frame currently defined.
The MAC Control Parameters field contains a 16-bit value that specifies the duration of the PAUSE event in units of
512-bit times. Valid values are 00-00 to FF-FF (hex). If an additional PAUSE frame arrives before the current
PAUSE time has expired, its parameter replaces the current PAUSE time, so a PAUSE frame with parameter zero
allows traffic to resume immediately.
A 42-byte reserved field (transmitted as all zeros) is required to pad the length of the PAUSE frame to the minimum
Ethernet frame size.
Preamble
(7-bytes)
AX88796B will inhibit transmit frames for a specified period of time if a PAUSE frame received and CRC is
correct. If a PAUSE request is received while a transmit frame is in progress, then the pause will take effect after the
transmitting is completed.
AX88796B base on “Rx Page Start Register” (CR page0 Offset 01h) and “Rx Page Stop Register”(CR page0 Offset
02h) to calculate and got the total of free page count can be used for store received packets. (One page equal to 256
bytes) The total of free page count will decrease when packets received. A programmable of high water
free-page-count in “Flow Control Register” (Offset 1Ah) used to measure the water level of receive buffer.
AX88796B use XOFF / XON flow-control method to avoid missing packet if receive buffer almost full. A XON
transmitting when the total of free page count equal to or less then “high water free-page-count”. A XOFF
transmitting when the total of free page count equal to or greater then (“high water free-page-count” + 6 pages).
Start Frame
Delimiter
(1-byte)
PAUSE frame
RX
TX
Dest. MAC
Address
(6-bytes)
= (01-80-C2-
00-00-01)
TX Flow Control
STOP
AX88796B
Packet
Source
MAC
Address
(6-bytes)
Fig - 6 TX / RX Flow control
Length/Type
(2-bytes)
= 802.3 MAC
Control
(88-08)
HOST
26
MAC Control
Opcode
(2-bytes)
= PAUSE
(00-01)
The total of
free pages count
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION
MAC Control
Parameters
(2-bytes)
= (00-00 to
FF-FF)
RX Flow Control
Packets in RX buffer
Programmable of free-page-count
6 pages
Reserved
(42-bytes)
= all zeros
High water mark
Low water mark
Start to generate XON
frame packet
generate XOFF frame
packet
Frame
Check
Sequence
(4-bytes)