AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 27

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

4.5 Big- and Little-endian Support
4.6 General Purpose Timer (GP Timer)
4.4.2 Half-Duplex Flow Control
Whenever the receive buffer becomes full crosses a certain threshold level, The MAC starts sending a Jam signal,
which will result in a collision. After sensing the collision, the remote station will back off its transmit ion.
AX88796B only generate this collision-based of back-pressure when it receives a new frame, in order to avoid any
late collisions.
A programmable of “Back-pressure Jam Limit count” (Offset 17h) is used for avoid HUB port partition due to many
continues of collisions. AX88796B will reset the “Back-pressure Jam Limit count” when either a transmitted or
received frame without collision. A back-pressure leakage allow when senses continue of collisions count up to
“Back-pressure Jam Limit count”, it will be no jamming one of receive frame even receive buffer is full.
AX88796B supports “Big-“ or “Little-endian” processor. To support big-endian processors, the hardware designer
must explicitly invert the layout of the byte lanes. In addition, for a 16-bit interface, the big-endian register must be
set correctly following the table below.
Additionally, please refer to Big-endian register (offset 1Eh), for additional information on status indication on big-
or little-endian modes.
AX88796B’s 16-bit Data Port (DP) read/write like a FIFO not rely on address pin. The “Even access” means the
first of access Data Port (DP) behind of remote read/write Command Register (CR). The second time access Data
Port (DP) is “Odd access” and then next is “Even access”, and so on.
Host can read bit-7 in “Device Status Register” (Offset 17h) to know the current of big- or little-endian types. The
default is Little-endian mode.
The programmable General Purpose Timer can be used to generate periodic host interrupts and the resolution of this
timer is 100us.
The GP timer is a 16-bit of register. GPT1 (CR page3 offset 0Fh) and GPT0 (CR page3 offset 0Eh) to compost this
16-bit of General Purpose Timer. This GP timer field of default value is FFFFh. Once set the General Purpose
Timer Enable (CR page3 Offset 0Dh) the GPT counts down until it reaches 0000h then update the a new pre-load
value into GPT, and continues counting.
The GPT interrupt has no status indicate in Interrupt Status Register (CR page0 offset 07h). The interrupt event will
keep active until host driver read Interrupt Status Register (CR page0 offset 07h) then clear GPT interrupt event.
MODE OFOPERATION AX88796B DATA PINS
Mode 0 Big-endian register (offset 1Eh) not equal to 0x0000h
Mode 0 Little-endian register (offset 1Eh) equal to 0x0000h (default)
Even access
Even access
Odd access
Odd access
SD[15:8]
Byte3
Byte1
Byte1
Byte3
Tab - 11 Byte Lane Mapping
SD[7:0]
Byte2
Byte0
Byte0
Byte2
27
DESCRIPTION
This mode can be used by 32-bit processors
operating with an external 16-bit bus.
This mode can also be used by native 16-bit
processors.
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION