AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 37

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

5.1.8 Number Of Collisions Register (NCR)
Page0 Offset 05H (Read)
5.1.9 Transmit Byte Count Register (TBCR1)
Page0 Offset 06H (Write)
5.1.10 Current Page Register (CPR)
Page0 Offset 06H (Read)
5.1.11 Interrupt Status Register (ISR)
Page0 Offset 07H (Read/Write)
Field
7:4
3:0
Field
7:0
Field
7:0
Field
7
6
5
4
3
2
1
0
-
TBCR1
CPR
OVW
TXE
RXE
PRX
Name
NCR
Name
Name
Name
RST
RDC
CNT
PTX
Description (Default = 00h)
Always zero
If no collisions are experienced during a transmission attempt, the COL bit of the TSR will
not be set and the contents of NCR will be zero. If there are excessive collisions, the ABT bit
in the TSR will be set and the contents of NCR will be zero. The NCR is cleared after the
TXP bit in the CR is set.
Description
Transmit Byte Count Register.
Description (Default = 4Dh)
The Buffer Management Logic as a backup register for reception uses this register
internally. CURR contains the address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive errors. This register is initialized
to the same value as PSTART and should not be written to again unless the controller is
Reset.
Description (Default = 80h)
Reset Status:
command is issued to the CR. Writing to this bit is no effect.
Remote DMA Complete
Counter Overflow
then reset its.
OVERWRITE: Set when receive buffer ring storage resources have been exhausted.
Transmit Error
Excessive collisions, Transmit over size and late collision.
Write this bit to high then reset it.
Receive Error
CRC error
Frame Alignment Error
Missed Packet
Write this bit to high then reset it.
Packet Transmitted
Packet Received
Set when AX88796B enters reset state (or a wake-up event) and cleared when a start
Set when remote DMA operation has been completed. Write this bit to high then reset it.
Set when MSB of one or more of the Tally Counters has been set. Write this bit to high
Write this bit to high then reset it.
Set when packet transmitted with one or more of the following errors
Indicates that a packet was received with one or more of the following errors
Indicates packet transmitted with no error
Write this bit to high then reset it.
Indicates packet received with no error.
Write this bit to high then reset it.
37
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION