AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 6

no-image

AX88796BLI

Manufacturer Part Number
AX88796BLI
Description
Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AX88796BLI
Manufacturer:
ASIX
Quantity:
20 000
2.0 Signal Description
2.1 Local CPU Bus Interface Signals Group
SA[4:0]
SA[5] or
FIFO_SEL
SD[15:0]
IRQ
CSn
RDn
WRn
IOIS16n
AEN or PSEN
All pin names with the “n” suffix are low-active signals.
The following abbreviations are used in following Tables.
I
O
I5
O5
T5
B5
4m
The following abbreviations are used in AX88796B pinout:
Signal
Output 1.8V
Output 3.3V with 5V tolerant
4mA driving strength
Input 1.8V
Input 3.3V with 5V tolerant
Tri-state with 5V tolerant
Bi-directional I/O, 3.3V with 5V tolerant
O5/T5/8m
B5/8m
T5/8m
I5/PD
Type
I5
I5
I5
I5
I5
46, 47, 48, 49,
27, 28, 29, 30,
31, 32, 33, 34,
35, 36, 37, 38,
39, 40, 41, 42
Pin No.
50
45
23
52
53
54
55
51
System Address: Signals SA[4:0] are address bus input lines. Used to
select internal CSR’s.
System Address or FIFO Select: When driven high, all accesses to the
AX88796B are to the RX or TX data buffer FIFO (DP).
AX88796B supports two kinds of Data Port for receiving/transmitting
packets from/to AX88796B. One is the PIO Data Port (offset 10h);
the other one is the SRAM-like Data Port (e.g. offset 800h ~ FFFh for
Samsung2440 processor as described in Appendix A4 of AX88796B
datasheet). The SRAM-like Data Port address range depends on
which address line of host processor is being connected to the address
line SA5/FIFO_SEL of AX88796B.
Software on host CPU can issue Single Data Read/Write command to
both PIO Data Port and SRAM-like Data Port. However, to use Burst
Data Read/Write commands, one has to use SRAM-like Data Port,
which requires SA5/FIFO_SEL (pin 45) of AX88796B connecting to
an upper address line of host CPU. Our reference schematic has
SA5/FIFO_SEL pin connected to upper address line for supporting
Burst Data Read/Write commands.
System Data Bus: Signals SD[15:0] constitute the bi-directional data
bus.
Programmable Interrupt request. Programmable polarity, source and
buffer types.
Can be configure by EEPROM auto-loader or BTCR (offset 15h)
Chip Select: Active low.
Read: Active low strobe to indicate a read cycle.
Write: Active low strobe to indicate a write cycle. This signal also
used to wakeup the AX88796B when it is in reduced power state.
address at the range corresponds to an I/O address to which the chip
responds, and the I/O port addressed is capable of 16-bit access.
Address Enable: When 186, ISA mode, this signal is active low to
access AX88796B.
PSEN: When 51 modes, this signal is active high to access
AX88796B.
16 Bit Port: For ISA bus used. The IOIS16n is asserted when the
6
8m
S
PU
PD
P
A
AX88796BLF / AX88796BLI
Analog
8mA driving strength
Schmitt trigger
Internal Pull Up 75Kohm
Internal Pull Down 75kohm
Power Pin
ASIX ELECTRONICS CORPORATION
Description

Related parts for AX88796BLI