AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 61

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

6.5 CPU Access MII Serial Management Interface
Basic Operation
The primary function of station management is to transfer control and status information about the PHY to a
management entity. This function is accomplished by the MDC clock input from MAC entity. The maximum
frequency is 2.5 MHz.
The Internal PHY address is fixed to 10h and the equivalent circuit is shown as below:
A specific set of registers and their contents (described in Tab - 19 MII Management Frames- field Description)
defines the nature of the information transferred across the MDIO interface. Frames transmitted on the MII
management interface will have the frame structure shown in Tab - 18 SMI Management Frame Format. The
order of bit transmission is from left to right. Note that reading and writing the management register must be
completed without interruption.
Read/Write
(R/W)
R
W
Field
Pre
ST
OP
PHYADD
REGAD
TA
DATA
IDLE
From Register
Offset 14h
Pre
1. . .1
1. . .1
Preamble. The PHY will accept frames with no preamble. This is indicated by a 1 in MR1 1, bit 6.
Start of Frame. The start of frame is indicated by a 01 pattern.
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is a 01.
PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity that is
attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for
each entity.
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY. The
first register address bit transmitted and received is the MSB of the address.
Turnaround. The turnaround time is a 2-bit time spacing between the register address field, and
the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a
write to the PHY, these bits is driven to 10 by the station. During a read, the MDIO is not
driven during the first bit time and is driven to a 0 by the PHY during the second bit time.
Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register
being addressed.
Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be
disabled and the PHY’s pull-up resistor will pull the MDIO line to logic 1.
MDO
MDC
MDI
ST
01
01
OP
10
01
Tab - 19 MII Management Frames- field Description
Tab - 18 SMI Management Frame Format
PHYAD
AAAAA
AAAAA
Fig - 9 SMI connections
MDC
RRRRR
RRRRR
REGAD
61
MDIO-OUT
Descriptions
TA
Z0
10
(Internal PHY)
AX88796BLF / AX88796BLI
DATA
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
ASIX ELECTRONICS CORPORATION
MDIO-IN
IDLE
Z
Z