AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 77

• Manufacturer Part Number: AX88796BLI
• Description: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

Appendix A4: co-work with 32-bit processor
Host Addr
A[11:0]
0
2
4
6
8
A
C
E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
An example, AX88796B co-work with Samsung 2440 processor. (32-bit processor with external 16-bit bus)
AX88796B’s bus setting as ISA mode. (Without external resister connect to EECS and EECK) Host can use burst
read mode, it is useful host processor increment its address when moving AX88796B received data.
Software on host CPU can issue Single Data Read/Write command to both PIO Data Port and SRAM-like Data Port.
However, to use Burst Data Read/Write commands, one has to use SRAM-like Data Port, which requires
SA5/FIFO_SEL (pin 45) of AX88796B connecting to an upper address line of host CPU. AX88796B with Samsung
2440 processor reference schematic has SA5/FIFO_SEL pin connected to upper address line (i.e. A11 of Samsung
2440) for supporting Burst Data Read/Write commands.
AX88796B supports two kinds of Data Port for receiving/transmitting packets from/to AX88796B. One is the PIO
Data Port (offset 10h); the other one is the SRAM-like Data Port (e.g. offset 800h ~ FFFh for Samsung2440
processor as described in below figure). The SRAM-like Data Port address range depends on which address line of
host processor is being connected to the address line SA5/FIFO_SEL of AX88796B.
Samsung2440
SD[15:8]
Offset 1
Offset 1
Offset 3
Offset 3
Offset 5
Offset 5
Offset 7
Offset 7
Offset 9
Offset 9
Offset B
Offset B
Offset D
Offset D
Offset F
Offset F
10 (DP)
X
Offset 13
Offset 13
Offset 15
Offset 15
Offset 17
Offset 17
WRn
RDn
A11
CSn
INT
A0
A1
A2
A3
A4
A5
Read
SD[7:0]
Offset 0
Offset 1
Offset 2
Offset 3
Offset 4
Offset 5
Offset 6
Offset 7
Offset 8
Offset 9
Offset A
Offset B
Offset C
Offset D
Offset E
Offset F
10 (DP)
X
Offset 12
Offset 13
Offset 14
Offset 15
Offset 16
Offset 17
AX88796B
CSR Offset
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10 (DP)
X
12
13
14
15
16
17
A0
A1
A2
A3
A4
A5/FIFO_SEL
CSn
RDn
WRn
IRQ
AEN/PSEN
77
Host Addr
A[11:0]
0
2
4
6
8
A
C
E
10
12
16
18
20
22
24
26
28
2A
2C
2E
14
1A
1C
1E
AX88796B
AX88796BLF / AX88796BLI
SD[15:8]
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
10 (DP)
X
no effect
no effect
no effect
no effect
no effect
no effect
ASIX ELECTRONICS CORPORATION
Write
SD[7:0]
To Offset 0
To Offset 1
To Offset 2
To Offset 3
To Offset 4
To Offset 5
To Offset 6
To Offset 7
To Offset 8
To Offset 9
To Offset A
To Offset B
To Offset C
To Offset D
To Offset E
To Offset F
10 (DP)
X
To Offset 12 12
To Offset 13 13
To Offset 14 14
To Offset 15 15
To Offset 16 16
To Offset 17 17
B
AX88796B
CSR Offset
0
1
2
3
4
5
6
7
8
9
A
C
D
E
F
10 (DP)
X