BC41B143AXX-IXB-E4 ETC1 [List of Unclassifed Manufacturers], BC41B143AXX-IXB-E4 Datasheet

no-image

BC41B143AXX-IXB-E4

Manufacturer Part Number
BC41B143AXX-IXB-E4
Description
BlueCore 4-ROM CSP EDR Single Chip Bluetooth v2.0 + EDR System
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
BC41B143A-ds-002Pd
Device Features
!
!
!
!
!
!
!
!
!
!
!
!
General Description
_äìÉ`çêÉQJolj=`pm is a single-chip radio and
baseband IC for Bluetooth 2.4GHz systems
including EDR to 3Mbits/s.
With the on-chip CSR Bluetooth software stack it
provides a fully compliant Bluetooth system to
v2.0 + EDR of the specification for data and voice
communications.
RF OUT
RF IN
BlueCore4-ROM CSP System Architecture
Fully Qualified Bluetooth v2.0 + EDR System
Enhanced Data Rate (EDR) compliant with
v2.0 of specification for both 2Mbits/s and
3Mbits/s modulation modes
Full-speed Bluetooth Operation with Full
Piconet Support
Scatternet Support
1.8V core, 1.7 to 3.6V I/O Split Rails
Ultra Low Power Consumption
Excellent Compatibility with Cellular
Telephones
Minimum External Components Required
Integrated 1.8V Linear Regulator
USB and UART Port to 3MBits/s
Support for 802.11 Co-existence
RoHS Compliant
Radio
GHz
2.4
Baseband
RAM
ROM
MCU
XTAL
DSP
This material is subject to CSR’s non-disclosure agreement
I/O
© Cambridge Silicon Radio Limited 2005
UART/USB
PCM
SPI
PIO
Production Information
Applications
!
!
!
!
BlueCore4-ROM CSP is designed to reduce the number
of external components required. This ensures that
production costs are minimised.
The device incorporates auto-calibration and built-in
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and device
firmware is fully compliant with the Bluetooth v2.0 + EDR
Specification (all mandatory and optional features).
To improve the performance of both Bluetooth and
802.11b/g co-located systems a wide range of
co-existence features are available including a variety of
hardware signalling: basic activity signalling and Intel
WCS activity and channel signalling.
_äìÉ`çêÉ»QJolj=`pm=bao
Cellular Handsets
Personal Digital Assistants (PDAs)
Digital cameras and other high-volume consumer
products
Space critical applications
Single Chip Bluetooth
v2.0 + EDR System
Product Data Sheet for
September 2005
BC41B143A
Page 1 of 89
®

Related parts for BC41B143AXX-IXB-E4

BC41B143AXX-IXB-E4 Summary of contents

Page 1

Device Features ! Fully Qualified Bluetooth v2.0 + EDR System ! Enhanced Data Rate (EDR) compliant with v2.0 of specification for both 2Mbits/s and 3Mbits/s modulation modes ! Full-speed Bluetooth Operation with Full Piconet Support ! Scatternet Support ! 1.8V ...

Page 2

... Contents 1 Status Information ......................................................................................................................................... 7 2 Key Features .................................................................................................................................................. 8 3 CSP Package Information ............................................................................................................................. 9 3.1 BlueCore4-ROM CSP Pinout Diagram .................................................................................................... 9 3.2 BC41B143AXX-IXF Device Terminal Functions .................................................................................... 10 4 Electrical Characteristics ............................................................................................................................ 13 4.1 Power Consumption .............................................................................................................................. 19 5 Radio Characteristics – Basic Data Rate ................................................................................................... 20 5.1 Temperature +20°C ............................................................................................................................... 20 5.1.1 Transmitter ................................................................................................................................. 20 5.1.2 Receiver ..................................................................................................................................... 22 5.2 Temperature -40°C................................................................................................................................ 24 5.2.1 Transmitter ................................................................................................................................. 24 5.2.2 Receiver ..................................................................................................................................... 24 5.3 Temperature -25°C................................................................................................................................ 25 5.3.1 Transmitter ................................................................................................................................. 25 5.3.2 Receiver ..................................................................................................................................... 25 5.4 Temperature +85° ...

Page 3

Memory Management Unit ......................................................................................................... 40 8.6.2 Burst Mode Controller ................................................................................................................ 40 8.6.3 Physical Layer Hardware Engine DSP....................................................................................... 40 8.6.4 RAM ........................................................................................................................................... 40 8.6.5 ROM........................................................................................................................................... 40 8.6.6 USB............................................................................................................................................ 41 8.6.7 Synchronous Serial Interface ..................................................................................................... 41 8.6.8 UART ......................................................................................................................................... 41 8.6.9 ...

Page 4

Reading from BlueCore4-ROM CSP.......................................................................................... 67 11.6.4 Multi-Slave Operation................................................................................................................. 67 11.7 Audio PCM Interface ............................................................................................................................. 68 11.7.1 PCM Interface Master/Slave ...................................................................................................... 68 11.7.2 Long Frame Sync....................................................................................................................... 69 11.7.3 Short Frame Sync ...................................................................................................................... 69 11.7.4 Multi Slot Operation.................................................................................................................... 70 11.7.5 GCI ...

Page 5

List of Figures Figure 3.1: BlueCore4-ROM CSP Package ............................................................................................................ 9 Figure 7.1: BlueCore4-ROM CSP Device Diagram for CSP Package .................................................................. 38 Figure 9.1: BlueCore HCI Stack ............................................................................................................................ 42 Figure 10.1: Basic Data Rate and Enhanced Data Rate Packet Types ................................................................ ...

Page 6

List of Tables Table 10.1: Data Rate Schemes ........................................................................................................................... 46 Table 10.2: 2-Bits Determine Phase Shift Between Consecutive Symbols ........................................................... 47 Table 10.3: 3-Bits Determine Phase Shift Between Consecutive Symbols ........................................................... 48 Table 11.1: PSKEY_TXRX_PIO_CONTROL Values ............................................................................................ 51 Table 11.2: ...

Page 7

Status Information The status of this Data Sheet is Advance Information. CSR Product Data Sheets progress according to the following format: Advance Information Information for designers concerning CSR product in development. All values specified are the target values of ...

Page 8

Key Features Radio ! Common TX/RX terminals simplify external matching and eliminates external antenna switch ! BIST minimises production test time. No external trimming is required in production ! Full RF reference designs are available ! Bluetooth v2.0 + ...

Page 9

CSP Package Information 3.1 BlueCore4-ROM CSP Pinout Diagram Figure 3.1: BlueCore4-ROM CSP Package This material is subject ...

Page 10

... BC41B143AXX-IXF Device Terminal Functions Radio Ball Pad Type RF_A E2 Analogue RF_B E1 Analogue AUX_DAC D2 Analogue Synthesiser and Ball Pad Type Oscillator XTAL_IN A3 Analogue XTAL_OUT B3 Analogue PCM Interface Ball Pad Type CMOS output, tri-statable PCM_OUT E4 with weak internal pull- down CMOS input, with weak ...

Page 11

Test and Debug Ball Pad Type CMOS input with weak RESETB E7 internal pull-up CMOS input with weak SPI_CSB G6 internal pull-up CMOS input with weak SPI_CLK G5 internal pull-down CMOS input with weak SPI_MOSI F6 internal pull-down CMOS output, ...

Page 12

Power Supplies and Ball Pad Type Control VREG_IN A2 Regulator input VDD_USB A5 VDD VDD_PIO G4 VDD VDD_PADS D6 VDD VDD_CORE C6 VDD VDD_LO B2 VDD VDD_RADIO C2 VDD VDD_ANA A4 VDD/Regulator output VSS_DIG C7 VSS VSS_PADS G3 VSS VSS_RADIO ...

Page 13

Electrical Characteristics Absolute Maximum Ratings Rating Storage temperature Supply voltage: VDD_RADIO, VDD_LO, VDD_ANA, and VDD_CORE Supply voltage: VDD_PADS, VDD_PIO and VDD_USB Supply voltage: VREG_IN Other terminal voltages Recommended Operating Conditions Operating Condition Operating temperature range (1) Guaranteed RF performance ...

Page 14

Input/Output Terminal Characteristics Linear Regulator Normal Operation Output voltage (I = 70mA / VREG_IN = 3.0V) load Temperature coefficient (1) Output noise Load regulation (I < 70mA) load (2) Settling time Maximum output current Output current: Minimum load current Input ...

Page 15

Input/Output Terminal Characteristics (Continued) Digital Terminals Input Voltage Levels 2.7V ≤ VDD ≤ 3.0V V input logic level low IL 1.7V ≤ VDD ≤ 1.9V V input logic level high IH Output Voltage Levels V output logic level low, OL ...

Page 16

Input/Output Terminal Characteristics (Continued) USB Terminals VDD_USB for correct USB operation Input threshold V input logic level low IL V input logic level high IH Input leakage current (1) < VDD_USB VSS_USB< Input capacitance I Output Voltage ...

Page 17

Input/Output Terminal Characteristics (Continued) Auxiliary DAC Resolution (1) Average output step size Output Voltage Voltage range (IO=0mA) Current range Minimum output voltage (IO=100μA) Maximum output voltage (IO=10mA) High Impedance leakage current Offset (1) Integral non-linearity Settling time (50pF load) Note: ...

Page 18

Input/Output Terminal Characteristics (Continued) Crystal Oscillator (1) Crystal frequency (2) Digital trim range (2) Trim step size Transconductance (3) Negative resistance External Clock (4) Input frequency (5) Clock input level Allowable jitter XTAL_IN input impedance XTAL_IN input capacitance Notes: VDD_CORE, ...

Page 19

Power Consumption Operation Mode Page scan, time interval 1.28s Inquiry & page scan ACL data transfer no traffic ACL data transfer with file transfer ACL data transfer no traffic ACL data transfer with file transfer ACL data transfer 40ms ...

Page 20

Radio Characteristics – Basic Data Rate 5.1 Temperature +20°C 5.1.1 Transmitter Radio Characteristics VDD = 1.8V (1)(2) Maximum RF transmit power Variation in RF power over temperature range with (4) compensation enabled (±) Variation in RF power over temperature ...

Page 21

Radio Characteristics VDD = 1.8V Frequency (GHz) 0.869 – 0.894 0.869 – 0.894 Emitted power in 0.925 – 0.960 cellular bands 1.570 – 1.580 measured at the unbalanced port of the balun. 1.805 – 1.880 Output power 1.930 – 1.990 ...

Page 22

Receiver Radio Characteristics VDD = 1.8V Sensitivity at 0.1% BER for all packet types Maximum received signal at 0.1% BER Continuous power required to block Bluetooth reception (for sensitivity of -67dBm with 0.1% BER) measured at the unbalanced port ...

Page 23

Radio Characteristics VDD = 1.8V Frequency (GHz) 0.824 – 0.849 Continuous power in cellular bands 0.824 – 0.849 required to block 0.880 – 0.915 Bluetooth reception (for sensitivity of -67dBm with 0.1% 1.710 – 1.785 BER) measured at the unbalanced ...

Page 24

Temperature -40°C 5.2.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F Adjacent channel transmit power F=F Δf1avg ...

Page 25

Temperature -25°C 5.3.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F Adjacent channel transmit power F=F Δf1avg ...

Page 26

Temperature +85°C 5.4.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F Adjacent channel transmit power F=F Δf1avg ...

Page 27

Temperature +105°C 5.5.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Adjacent channel transmit power F=F Adjacent channel transmit power F=F Δf1avg ...

Page 28

Radio Characteristics – Enhanced Data Rate 6.1 Temperature +20°C 6.1.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power (3) Relative transmit power π/4 DQPSK (3) Max carrier frequency stability w 0 π/4 DQPSK (3) Max carrier ...

Page 29

Class 2 RF transmit power range, Bluetooth v2.0 + EDR specification. (3) Measurement methods are in accordance with the Bluetooth v2.0 + EDR specification. (4) Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency ...

Page 30

Temperature -40°C 6.2.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power (3) Relative transmit power π/4 DQPSK (3) Max carrier frequency stability w 0 π/4 DQPSK (3) Max carrier frequency stability w i π/4 DQPSK (3) ...

Page 31

Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. (5) The Bluetooth specification values are for 8DPSK modulation three exceptions are allowed in the Bluetooth v2.0 + EDR specification. BlueCore4 is ...

Page 32

Temperature -25°C 6.3.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power (3) Relative transmit power π/4 DQPSK (3) Max carrier frequency stability w 0 π/4 DQPSK (3) Max carrier frequency stability w i π/4 DQPSK (3) ...

Page 33

Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. (5) The Bluetooth specification values are for 8DPSK modulation three exceptions are allowed in the Bluetooth v2.0 + EDR specification. BlueCore4 is ...

Page 34

Temperature +85°C 6.4.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power (3) Relative transmit power π/4 DQPSK (3) Max carrier frequency stability w 0 π/4 DQPSK (3) Max carrier frequency stability w i π/4 DQPSK (3) ...

Page 35

The Bluetooth specification values are for 8DPSK modulation three exceptions are allowed in the Bluetooth v2.0 + EDR specification. BlueCore4 is guaranteed to meet the ACP performance as specified by the Bluetooth v2.0 + EDR specification. 6.4.2 ...

Page 36

Temperature +105°C 6.5.1 Transmitter Radio Characteristics VDD = 1.8V (1) Maximum RF transmit power (3) Relative transmit power π/4 DQPSK (3) Max carrier frequency stability w 0 π/4 DQPSK (3) Max carrier frequency stability w i π/4 DQPSK (3) ...

Page 37

Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift. (5) The Bluetooth specification values are for 8DPSK modulation three exceptions are allowed in the Bluetooth v2.0 + EDR specification. BlueCore4 is ...

Page 38

Device Diagram VDD_USB VDD_PIO TEST_EN RESETB VDD_PADS VDD_CORE VDD_ANA VREG_IN VDD_LO XTAL_OUT XTAL_IN VDD_RADIO Figure 7.1: BlueCore4-ROM CSP Device Diagram for CSP Package This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited ...

Page 39

Description of Functional Blocks 8.1 RF Receiver The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input ...

Page 40

Clock Input and Generation The reference clock for the system is generated from a TCXO or crystal input between 8MHz and 40MHz. All internal reference clocks are generated using a phase locked loop, which is locked to the external ...

Page 41

USB This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices. BlueCore4-ROM CSP acts as a USB peripheral, responding to requests from a master host controller such as a PC. 8.6.7 Synchronous ...

Page 42

CSR Bluetooth Software Stacks BlueCore4-ROM CSP is supplied with Bluetooth v2.0 + EDR compliant stack firmware which runs on the internal RISC microcontroller. The BlueCore4-ROM CSP software architecture allows Bluetooth processing and the application program to be shared in ...

Page 43

Optional v2.0 + EDR functionality supported: ! AFH as Master and automatic channel classification ! Fast connect – interlaced inquiry and page scan plus RSSI during inquiry ! Extended SCO (eSCO), eV3 + CRC, eV4, eV5 ! SCO handle ! ...

Page 44

Key Features of the HCI Stack - Extra Functionality The firmware extends the standard Bluetooth functionality with the following features: ! Supports BlueCore Serial Protocol (BCSP) – a proprietary, reliable alternative to the standard Bluetooth UART Host Transport Provides ...

Page 45

BCHS Software BlueCore Embedded Host Software is designed to enable CSR customers to integrate Bluetooth functionality into embedded products quickly, cheaply and with low risk. BCHS is developed to work with CSR's family of BlueCore ICs. BCHS is intended ...

Page 46

Enhanced Data Rate Enhanced Data Rate (EDR) has been introduced to provide 2x and 3x higher layers of the Bluetooth stack. BlueCore4-ROM supports both of the new data rates and is compliant with the Bluetooth v2.0 + EDR specification. ...

Page 47

Figure 10.2: π/4 DQPSK Constellation Pattern Bit Pattern Table 10.2: 2-Bits Determine Phase Shift Between Consecutive Symbols 10.3 Enhanced Data Rate 8DPSK 3x data rate modulation uses eight phase differential phase shift keying (8DPSK). Each symbol ...

Page 48

Figure 10.3: 8DPSK Constellation Pattern Bit Pattern 000 001 011 010 110 111 101 100 Table 10.3: 3-Bits Determine Phase Shift Between Consecutive Symbols This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd 011 001 100 101 ...

Page 49

Device Terminal Descriptions 11.1 RF_A and RF_B RF_A and RF_B form a complementary balanced pair. On transmit, their outputs are combined using a balun into the single-ended output required for the antenna. Similarly, on receive their input signals are ...

Page 50

Transmit RF Power Control for Class 1 Applications An 8-bit voltage DAC (AUX_DAC) can be used to control the amplification level of an external PA for Class 1 operation. The DAC output is derived from the on-chip band gap ...

Page 51

Control of External RF Components A PS Key, PSKEY_TXRX_PIO_CONTROL, controls external RF components such as a switch, an external external LNA. PIO[0], PIO[1] and the AUX_DAC can be used for this, as described in Table 11.1. ...

Page 52

XTAL_IN Impedance in External Mode The impedance of the XTAL_IN will not change significantly between operating modes, typically only 10fF. When transitioning from deep sleep to an active state a spike 1pC may be measured. For ...

Page 53

Actual Allowable Clock Presence Delay on XTAL_IN vs. PSKey Setting 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0 5.0 Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting 11.2.5 Input Frequencies and PS Key Settings BlueCore4-ROM ...

Page 54

Crystal Oscillator (XTAL_IN, XTAL_OUT) The BlueCore4-ROM CSP RF local oscillator and internal digital clocks are derived from the reference clock at the BlueCore4-ROM CSP XTAL_IN input. This reference may be either an external clock or from a crystal connected ...

Page 55

Figure 11.6 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors. Figure 11.6: Crystal Equivalent Circuit The resonant frequency can be trimmed with the ...

Page 56

The frequency trim is described by Equation 11.5. Δ Where F is the crystal frequency and pullability is a crystal parameter with units of ppm/pF. Total trim range times the value above. If not specified, the pullability ...

Page 57

This formula shows the negative resistance of the BlueCore4-ROM CSP driver as a function of its drive strength. The value of the driver negative resistance can be easily measured by placing an additional resistance in series with the crystal. The ...

Page 58

Gm Typical Gm Minimum Gm Maximum Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting Note: Drive level is set by PS Key PSKEY_XTAL_LVL. This material ...

Page 59

Typical Minimum Maximum Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting Crystal parameters: Crystal frequency 16MHz (Refer to your software build release note for frequencies supported) Crystal ...

Page 60

UART Interface BlueCore4-ROM CSP UART interface provides a simple mechanism for communicating with other serial devices (1) using the RS232 standard . Four signals are used to implement the UART function: ! UART_TX ! UART_RX ! UART_RTS ! UART_CTS ...

Page 61

The UART interface is capable of resetting BlueCore4-ROM CSP upon reception of a break signal. A break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 11.10 than the value, defined ...

Page 62

UART Bypass RXD CTS RTS TXD Host Processor Test Interface Figure 11.11: UART Bypass Architecture 11.4.2 UART Configuration while RESETB is Active The UART interface for BlueCore4-ROM CSP while the IC is being held in reset is tri-stated. This ...

Page 63

USB Interface BlueCore4-ROM CSP devices contain a full speed (12Mbits/s) USB interface that is capable of driving a USB cable directly. No external USB transceiver is required. The device operates as a USB peripheral, responding to requests from a ...

Page 64

BlueCore4-ROM CSP Figure 11.12: USB Connections for Self Powered Mode The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding PIO number. 11.5.5 Bus-powered Mode In bus-powered ...

Page 65

Identifier R s Table 11.7: USB Interface Component Values 11.5.6 Suspend Current All USB devices must permit the USB controller to place them in a USB Suspend mode. While in USB Suspend, bus-powered devices must not draw more than 0.5mA ...

Page 66

USB Compliance BlueCore4-ROM CSP is designed to be compatible with and adhere to the USB specification v1.1, details of which are available from http://www.usb.org. The specification contains valuable information on aspects such as PCB track impedance, supply inrush current ...

Page 67

Writing to BlueCore4-ROM CSP To write to BlueCore4-ROM CSP, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-bit address (A[15:0]). The next 16 bits (D[15:0]) clocked in on SPI_MOSI are written to the location set ...

Page 68

Audio PCM Interface Pulse Code Modulation (PCM standard method used to digitise audio (particularly voice) patterns for transmission over digital communication channels. Through its PCM interface, BlueCore4-ROM CSP has hardware support for continual transmission and reception of ...

Page 69

Figure 11.18: BlueCore4-ROM CSP as PCM Interface Slave 11.7.2 Long Frame Sync Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge ...

Page 70

As with Long Frame Sync, BlueCore4-ROM CSP samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT can be configured to be high impedance on the falling edge of PCM_CLK in the LSB position ...

Page 71

Slots and Sample Formats BlueCore4-ROM CSP can receive and transmit on any selection of the first four slots following each sync pulse. Slot durations can be either clock cycles. Durations of 8 clock cycles can only ...

Page 72

PCM Timing Information Symbol Parameter f PCM_CLK frequency mclk - PCM_SYNC frequency (1) t PCM_CLK high mclkh (1) t PCM_CLK low mclkl - PCM_CLK jitter Delay time from PCM_CLK high to PCM_SYNC t dmclksynch high t Delay time from ...

Page 73

PCM_SYNC t PCM_CLK t dmclkpout PCM_OUT t supinclkl PCM_IN Figure 11.24: PCM Master Timing Long Frame Sync t dmclksynch PCM_SYNC PCM_CLK PCM_OUT PCM_IN Figure 11.25: PCM Master Timing Short Frame Sync This material is subject to CSR’s non-disclosure ...

Page 74

PCM Slave Timing Symbol Parameter f PCM clock frequency (Slave mode: input) sclk f PCM clock frequency (GCI mode) sclk t PCM_CLK low time sclkl t PCM_CLK high time sclkh t Hold time from PCM_CLK low to PCM_SYNC high ...

Page 75

PCM_CLK t t susclksynch hsclksynch PCM_SYNC PCM_OUT PCM_IN Figure 11.27: PCM Slave Timing Short Frame Sync 11.7.10 PCM_CLK and PCM_SYNC Generation BlueCore4-ROM CSP has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating these signals ...

Page 76

PCM Configuration The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG. The following tables describe these PS Keys. The default for PSKEY_PCM_CONFIG32 is 0x00800000. long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal ...

Page 77

Name (Continued) Bit Position CNT_LIMIT [12:0] CNT_RATE [23:16] SYNC_LIMIT [31:24] Table 11.12: PSKEY_PCM_LOW_JITTER_CONFIG Description 11.8 I/O Parallel Ports Thirteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[10:8] and PIO[3:0] are powered from VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO[0] ...

Page 78

I C Master PIO[8:6] can be used to form an interface. The interface is driven by “bit banging” these PIO pins using software. Therefore it is suited only to relatively slow functions such as driving a dot matrix ...

Page 79

Resetting BlueCore4-ROM CSP BlueCore4-ROM CSP can be reset from several sources: ! the RESETB pin ! power on reset ! a UART break condition ! via a software configured watchdog timer The RESETB pin is an active low reset ...

Page 80

Status after Reset The state of the IC after a reset is as follows: (1) ! Warm Reset : Baud rate and RAM data typically remain available, depending on firmware configuration (2) Cold Reset : Baud rate and RAM ...

Page 81

Application Schematic Figure 12.1: Application Circuit for CSP Package This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Application Schematic Page ...

Page 82

Package Dimensions Figure 13.1: BlueCore4-ROM CSP Package Dimensions This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Production Information © Cambridge Silicon Radio Limited 2005 Package Dimensions Page ...

Page 83

... Minimum Order Quantity 2kpcs taped and reeled This material is subject to CSR’s non-disclosure agreement BC41B143A-ds-002Pd Package Shipment Size Method 3.8 x 4.0 x 0.7mm Tape and reel Production Information © Cambridge Silicon Radio Limited 2005 Ordering Information Order Number BC41B143AXX-IXB-E4 Page ...

Page 84

Contact Information CSR UK Cambridge Business Park Cowley Road Cambridge, CB4 0WZ United Kingdom Tel: +44 (0) 1223 692 000 Fax: +44 (0) 1223 692 001 e-mail: sales@csr.com CSR Korea 2nd floor, Hyo-Bong Building 1364-1, SeoCho-dong Seocho-gu Seoul 137-863 ...

Page 85

Document References Document Specification of the Bluetooth system Universal Serial Bus Specification 2 Selection EEPROMS for Use with BlueCore EDR RF Test Specification RF Prototyping Specification for Enhanced Data Rate IP BlueCore Power Saving Modes This ...

Page 86

Terms and Definitions π/4 DQPSK pi/4 rotated Differential Quaternary Phase Shift Keying 8DPSK 8-phase Differential Phase Shift Keying AC Alternating Current ACL Asynchronous ConnectionLess, a Bluetooth data packet type ADC Analogue to Digital Converter AFH Adaptive Frequency Hopping AGC Automatic ...

Page 87

ISDN Integrated Services Digital Network ISM Industrial, Scientific and Medical ksamples/s kilosamples per second L2CAP Logical Link Control and Adaptation Protocol (protocol layer) LC Link Controller LED Light Emitting Diode LMP Link Manager Protocol LNA Low Noise Amplifier LSB Least-Significant ...

Page 88

TX Transmit or Transmitter UART Universal Asynchronous Receiver Transmitter UHCI Universal Host Control Interface USB Universal Serial Bus or Upper Side Band (depending on context) VCO Voltage Controlled Oscillator VFBGA Very Fine Ball Grid Array W-CDMA Wideband Code Division Multiple ...

Page 89

Document History Date Revision Reason for Change Original publication of Advance Information Product Data Sheet (CSR reference FEB 05 a BC41B143A-ds-001Pa). Change to section 2 Key Features and 3.2 UART_RX and UART_CTS (CSR MAR 05 b reference BC41B143A-ds-002Pb). Updated Auxiliary ...

Related keywords