MN85571AC PANASONIC [Panasonic Semiconductor], MN85571AC Datasheet
MN85571AC
Related parts for MN85571AC
MN85571AC Summary of contents
Page 1
... LSIs for DVD MN85571AC Single-Chip Audio/Video MPEG2 Encoder Overview The MN85571AC is an audio/video encoder that performs video compression in conformance with the ISO/IEC 13818-2 (MPEG2 video) and ISO/IEC 11172-2 (MPEG1 video) standards and audio compression in conformance with * the Dolby Digital system. It also can multiplex the compressed audio and video signals. ...
Page 2
... Note) The MN85571AC includes two RISC microcontrollers (for video encoding and data multiplexing) and one DSP for audio encoding. The microcode for these two RISC microcontrollers must be downloaded to the on-chip instruction memory before the MN85571AC is used. The DSP microcode is stored in on-chip ROM, and does not need to be downloaded ...
Page 3
... Internal Resource Mapping The MN85571AC has two types of internal resources that are accessed by the external host with different methods. 1) Direct addressing resources (registers only) These resources are mainly used for controlling this device and indicating the internal state of the device. These are 16-bit registers ...
Page 4
... MN85571AC Internal Resource Mapping (continued) 2. Indirect addressing resources (registers and initial load memory) These internal resources are accessed by storing the address of the indirect addressing resource in the INADR0 indirect access address register and reading or writing the INDAT0 indirect access data register. Other than the regis- ters used for communication with the external host and the SRISC, these resources can only be accessed in the slave state ...
Page 5
... MA6 203 MA7 204 3.3V-VDD 205 MA8 206 MA9 207 GND 208 Note) The same signal must be input to both the NRST and TRST pins. (TOPVIEW) SDD00023AEM MN85571AC 104 GND 103 HD15 102 HD14 101 HD13 100 3.3V-VDD 99 HD12 98 HD11 97 HD10 96 1 ...
Page 6
... MN85571AC Signal and Control Timing Signal Overview The MN85571AC I/O signals can be classified by function as shown below. See the Pin Descriptions section for details on these signals. All signal pins conform to the LVTTL standard. Clock SCLK NRST Control TRST BUSY VCLK Video I/F VIN[7:0] HA[3:0] HD[15:0] NHCS ...
Page 7
... Code output pin initial state control External memory (SDRAM) clock output Clock input for data transfer between external memory and this product External memory (SDRAM) CKE output External memory (SDRAM) chip select output External memory (SDRAM) RAS output External memory (SDRAM) CAS output SDD00023AEM MN85571AC 7 ...
Page 8
... MN85571AC Pin Descriptions (continued) Type Pin Name I/O SDRAM I/F NMWE O SDRAM I/F MDQM O SDRAM I/F MA[13:0] O SDRAM I/F MDQ[31:0] I/O Power AVDD Power AGND Power 3.3V-VDD Power 1.8V-VDD Power GND 8 External memory (SDRAM) write enable output External memory (SDRAM) data output buffer control External memory (SDRAM) address output ...
Page 9
... V to 3.6 V AVDD 3 3.6 V DUTY: 50% 10 Jitter: 50 ppm VCLK 3.3V-VDD 3 3.6 V DUTY: 50% 10 Jitter: 50 ppm RCLKI 3.3V-VDD 3 3.6 V DUTY: 50% 10% DMACLK 3.3V-VDD 3 3.6 V DUTY: 50% 10% PCKI 3.3V-VDD 3 3.6 V DUTY: 50% 10% SDD00023AEM MN85571AC Unit 0.3 (Upper limit: 4.6) 0.3 (Upper limit: 4. Min Typ Max 3.0 3.3 3.6 1.65 1.80 1.95 3.0 3.3 3 27.0 27 ...
Page 10
... MN85571AC Interfaces 1. Host interface Accesses to this product’s internal resources from an external host take place using the host interface block (HIF). There are two techniques for accessing resources over the host interface as follows. 1) Direct addressing access 2) Indirect addressing access 1) Direct addressing access ...
Page 11
... NHCS rising edge time from NHWE rising edge HD[15:0] valid data hold time from the NHWE rising edge t wcyc Valid Data t wadcs t adwe t weset Valid Data "H" Item SDD00023AEM MN85571AC t wcsad t wecs t wead t wdhd "Hi-Z" Symbol Min Typ Max t 200 ...
Page 12
... MN85571AC Interfaces (continued) 1. Host interface (continued) 2) Indirect addressing access [Read] (1) The indirect address value is written to INADR0 (HA[3:0] = $6). This sets the indirect address. (2) Data is read from INDAT0 (HA[3:0] = $8). At this time the data at the address set in INADR0 is read out over this device's internal bus, although it appears to be read out from INDAT0. This completes the read operation. ...
Page 13
... MHz maximum CDO[7:0], CDREADY, RCLKO 3 RCLKI, IPIC, (VOB) 6.75 MHz, 3.375 MHz HD[15:0], NHDREQ, DMACLK NHDACK, DMACLK 33 MHz maximum HD[15:0], NHCS, HA[3:0], Clock signal not NHRE, NHWE, NHDREQ required SDD00023AEM MN85571AC Output data format MSB first MSB first Big Endian/ Little Endian Big Endian/ Little Endian 13 ...
Page 14
... MN85571AC Interfaces (continued) 4. Video data input interface Interface pin descriptions Pin Name I/O VIN[7:0] I Video data input Video data must be input in synchronization with the video data input clock (VCLK). The format of the input video data must be ITU-R BT.656 (level D1, 4:2:2). VCLK I Video data input clock input The video data input to this product assumes that the input signal has been time base corrected (TBC) in the stage prior to this product ...
Page 15
... External memory address output MDQ[ I/O External memory data I/O (These pins have built-in pull-up resistors.) MCKE O External memory CKE output Package Dimensions (Unit: mm) LQFP208-P-2828 (Lead-free package) 156 157 208 1 (1.25) Seating plane Description 30.00 ±0.20 28.00 ±0.10 105 104 53 52 0.50 0.20 ±0.05 0.08 M 0.10 SDD00023AEM MN85571AC (1.00 0.50 ±0.20 15 ...
Page 16
... No part of this material may be reprinted or reproduced by any means without written permission from our company. Please read the following notes before using the datasheets A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. ...