9248AG-192LFT Integrated Device Technology, 9248AG-192LFT Datasheet

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9248AG-192LFT

Manufacturer Part Number
9248AG-192LFT
Description
ic,9248ag-192lft
Manufacturer
Integrated Device Technology
Datasheet
Recommended Application:
Transmeta
Output Features:
Features:
Skew Characteristics:
Block Diagram
CPU3.3V_2.5V#sel
0540F—10/27/05
1CPU(2.5V or 3.3V selectable) up to 66.6MHz &
overclocking of 66MHz.
6 PCI (3.3V) @ 33.3MHz (all are free running
selectable).
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Supports Spread Spectrum modulation for CPU and
PCI clocks, default -0.4 downspread.
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-pin TSSOP package, 4.40mm (173mil).
CPU – CPU <175ps
PCI – PCI < 500ps
CPU(early) – PCI = 1.5ns – 4ns.
CPU_STOP#
PCI_STOP#
SEL48_24#
SEL66/60#
Frequency Timing Generator for Transmeta Systems
SDATA
SCLK
PD#
X2
X1
Integrated
Circuit
Systems, Inc.
XTAL
OSC
Spectrum
PLL2
Spread
Control
Config.
PLL1
Logic
Reg.
DIVDER
DIVDER
CPU
PCI
/ 2
Stop
Stop
6
48MHz
24_48MHz
PCICLK (5:0)
CPUCLK0
REF
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (5:0)
VDD48, GND48 = 48MHz (1:0)
GNDREF
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
VDDPCI
SDATA
SCLK
PD#
Pin Configuration
X1
X2
28-Pin TSSOP
10
11
12
13
14
1
2
3
4
5
6
7
8
9
ICS9248-192
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDREF
REF
CPU_STOP#
VDDLCPU
GNDLCPU
CPUCLK0
PCI_STOP#
GND_Core
VDD_Core
SEL66/60#
VDD48
GND48
48MHz/CPU3.3v_2.5V#sel
24-48MHz/Sel48_24#

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9248AG-192LFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. Frequency Timing Generator for Transmeta Systems Recommended Application: Transmeta Output Features: • 1CPU(2.5V or 3.3V selectable 66.6MHz & overclocking of 66MHz. • 6 PCI (3.3V) @ 33.3MHz (all are free running selectable). • 1 ...

Page 2

ICS9248-192 Pin Descriptions Pin number Pin name 1 GNDREF PD# 12, 11, 10 PCICLK (5:0) 8 GNDPCI 9 VDDPCI Sel48_24# 15 24_48MHz 13 SDATA 14 SCLK CPU3.3-2.5# 16 48MHz 17 GND48 18 ...

Page 3

CPU Select Functions Power Management Clock Enable Configuration C ...

Page 4

ICS9248-192 General I The information in this section assumes familiarity with I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a ...

Page 5

Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit2 Bit7 Bit6 Bit5 Bit FS4 FS3 FS2 FS1 ...

Page 6

ICS9248-192 Byte 1: PCI Stop ...

Page 7

CPU_STOP# Timing Diagram CPUSTOP asychronous input to the clock synthesizer used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-192. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) ...

Page 8

ICS9248-192 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal is synchronized internally ...

Page 9

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . ...

Page 10

ICS9248-192 Electrical Characteristics - CPUCLK 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B ...

Page 11

Electrical Characteristics - 48MHz 70° 3 VDDL = 2.5V, +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low ...

Page 12

ICS9248-192 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS9248yG-192LF-T Example: ICS XXXX PPP 0540F—10/27/05 In Millimeters SYMBOL COMMON DIMENSIONS MIN 0.05 A2 0.80 b 0.19 ...

Page 13

Revision History Rev. Issue Date Description F 10/27/2005 Added LF to Ordering Information 0540F—10/27/05 13 ICS9248-192 Page # 12 ...

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